I agree with your idea completely. One big disadvantage of projects from opencores.org is that many of them are lack of thorough verification. Bugs are associated with them. Python has its merit that it is an object oriented programming language and nowadays object oriented idea is widely applied in SoC verification. It might be possible that we can build a new verification methodology using MyHDL. I will try it to see the possibility.
----- Original Message -----
From: Jan Decaluwe <jan@...>
Date: Wednesday, May 20, 2009 3:40 pm
Subject: Re: [myhdl-list] new example for MyHDL
> Xiang Li wrote:
> > Hello all, I am a new user of MyHDL project. MyHDL is really a
> > project, which is ideal for software guys who are familiar
> with python
> > and trying to do hardware development . I just wrote a
> miniuart project
> > using MyHDL(rewrote from the source code downloaded from
> > website), for those novices who just come to the hardware
> world, it is a
> > very good example for you.
> Actually this may be a very good idea to combine learning by newbies
> and creating actual value: Redo opencores.org in MyHDL! I see a
> number of advantages:
> * a large set of examples to choose from, at various complexity levels
> * newbies have a clear spec, in the form of the exising implementation
> * I'm sure many projects can be improved, especially in the area of
> verification - MyHDL modeling might really help here
> * the end result also gives something back to the community, as you
> would now be able to use the core in 3 HDLs thanks to
> conversion. The fact that all cores would be available in
> both VHDL and
> Verilog might be very interesting to opencores users.
> I guess it's OK to use the existing opencores.org infrastructure
> to publish MyHDL cores.
> Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
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