Update of /cvsroot/mspgcc/msp430-libc/include/msp430
In directory 23jxhf1.ch3.sourceforge.com:/tmp/cvs-serv29161/include/msp430
Added Files:
gpio_5xxx.h mpy32.h sys.h wdt_a.h
Log Message:
5xxx headers:
- sys, wdt_a, mpy32, gpio added
msp430x47xx.h:
- multiplier changed to mpy32
gcrt0.S:
- 430X2 core interrupt vectors table added
--- NEW FILE: gpio_5xxx.h ---
#ifndef __MSP430_HEADERS_GPIO_5XXX_H
#define __MSP430_HEADERS_GPIO_5XXX_H
/* gpio_5xxx.h
*
* mspgcc project: MSP430 device headers
* Hardware 32-bit multiplier
*
* (c) 2008 by Sergey A. Borshch <sb-sf@...>
* Originally based in MSP430F543x datasheet (slas609)
* and MSP430x5xx Family User's Guide (slau208).
*
* $Id: gpio_5xxx.h,v 1.1 2008/12/07 22:45:57 sb-sf Exp $
*/
/* Switches:
__MSP430_PORT1_BASE__ - base address of PORT1 module. PORT1 present in device if defined
__MSP430_PORT2_BASE__ - base address of PORT2 module. PORT2 present in device if defined
__MSP430_PORT3_BASE__ - base address of PORT3 module. PORT3 present in device if defined
__MSP430_PORT4_BASE__ - base address of PORT4 module. PORT4 present in device if defined
__MSP430_PORT5_BASE__ - base address of PORT5 module. PORT5 present in device if defined
__MSP430_PORT6_BASE__ - base address of PORT6 module. PORT6 present in device if defined
__MSP430_PORT7_BASE__ - base address of PORT7 module. PORT7 present in device if defined
__MSP430_PORT8_BASE__ - base address of PORT8 module. PORT8 present in device if defined
__MSP430_PORT9_BASE__ - base address of PORT9 module. PORT9 present in device if defined
__MSP430_PORT10_BASE__ - base address of PORT10 module. PORT10 present in device if defined
__MSP430_PORT11_BASE__ - base address of PORT11 module. PORT11 present in device if defined
__MSP430_PORTJ_BASE__ - base address of PORTJ module. PORTJ present in device if defined
*/
#if defined(__MSP430_PORT1_BASE__)
#define P1IN_ __MSP430_PORT1_BASE__ + 0x00 /* Port 1 Input */
sfrb(P1IN, P1IN_);
#define P1OUT_ __MSP430_PORT1_BASE__ + 0x02 /* Port 1 Output */
sfrb(P1OUT, P1OUT_);
#define P1DIR_ __MSP430_PORT1_BASE__ + 0x04 /* Port 1 Direction */
sfrb(P1DIR, P1DIR_);
#define P1REN_ __MSP430_PORT1_BASE__ + 0x06 /* Port 1 Resistor enable */
sfrb(P1REN, P1REN_);
#define P1DS_ __MSP430_PORT1_BASE__ + 0x08 /* Port 1 Drive strength */
sfrb(P1DS, P1DS_);
#define P1SEL_ __MSP430_PORT1_BASE__ + 0x0A /* Port 1 Selection */
sfrb(P1SEL, P1SEL_);
#define P1IV_ __MSP430_PORT1_BASE__ + 0x0E /* Port 1 Interrupt vector word */
sfrb(P1IV, P1IV_);
#define P1IES_ __MSP430_PORT1_BASE__ + 0x18 /* Port 1 Interrupt Edge Select */
sfrb(P1IES, P1IES_);
#define P1IE_ __MSP430_PORT1_BASE__ + 0x1A /* Port 1 Interrupt Enable */
sfrb(P1IE, P1IE_);
#define P1IFG_ __MSP430_PORT1_BASE__ + 0x1C /* Port 1 Interrupt Flag */
sfrb(P1IFG, P1IFG_);
#endif
#if defined(__MSP430_PORT2_BASE__)
#define P2IN_ __MSP430_PORT2_BASE__ + 0x01 /* Port 2 Input */
sfrb(P2IN, P2IN_);
#define P2OUT_ __MSP430_PORT2_BASE__ + 0x03 /* Port 2 Output */
sfrb(P2OUT, P2OUT_);
#define P2DIR_ __MSP430_PORT2_BASE__ + 0x05 /* Port 2 Direction */
sfrb(P2DIR, P2DIR_);
#define P2REN_ __MSP430_PORT2_BASE__ + 0x07 /* Port 2 Resistor enable */
sfrb(P2REN, P2REN_);
#define P2DS_ __MSP430_PORT2_BASE__ + 0x09 /* Port 2 Drive strength */
sfrb(P2DS, P2DS_);
#define P2SEL_ __MSP430_PORT2_BASE__ + 0x0B /* Port 2 Selection */
sfrb(P2SEL, P2SEL_);
#define P2IV_ __MSP430_PORT2_BASE__ + 0x1E /* Port 2 Interrupt vector word */
sfrb(P2IV, P2IV_);
#define P2IES_ __MSP430_PORT2_BASE__ + 0x19 /* Port 2 Interrupt Edge Select */
sfrb(P2IES, P2IES_);
#define P2IE_ __MSP430_PORT2_BASE__ + 0x1B /* Port 2 Interrupt Enable */
sfrb(P2IE, P2IE_);
#define P2IFG_ __MSP430_PORT2_BASE__ + 0x1D /* Port 2 Interrupt Flag */
sfrb(P2IFG, P2IFG_);
#endif
#if defined(__MSP430_PORT3_BASE__)
#define P3IN_ __MSP430_PORT3_BASE__ + 0x00 /* Port 3 Input */
sfrb(P3IN, P3IN_);
#define P3OUT_ __MSP430_PORT3_BASE__ + 0x02 /* Port 3 Output */
sfrb(P3OUT, P3OUT_);
#define P3DIR_ __MSP430_PORT3_BASE__ + 0x04 /* Port 3 Direction */
sfrb(P3DIR, P3DIR_);
#define P3REN_ __MSP430_PORT3_BASE__ + 0x06 /* Port 3 Resistor enable */
sfrb(P3REN, P3REN_);
#define P3DS_ __MSP430_PORT3_BASE__ + 0x08 /* Port 3 Drive strength */
sfrb(P3DS, P3DS_);
#define P3SEL_ __MSP430_PORT3_BASE__ + 0x0A /* Port 3 Selection */
sfrb(P3SEL, P3SEL_);
#endif
#if defined(__MSP430_PORT4_BASE__)
#define P4IN_ __MSP430_PORT4_BASE__ + 0x01 /* Port 4 Input */
sfrb(P4IN, P4IN_);
#define P4OUT_ __MSP430_PORT4_BASE__ + 0x03 /* Port 4 Output */
sfrb(P4OUT, P4OUT_);
#define P4DIR_ __MSP430_PORT4_BASE__ + 0x05 /* Port 4 Direction */
sfrb(P4DIR, P4DIR_);
#define P4REN_ __MSP430_PORT4_BASE__ + 0x07 /* Port 4 Resistor enable */
sfrb(P4REN, P4REN_);
#define P4DS_ __MSP430_PORT4_BASE__ + 0x09 /* Port 4 Drive strength */
sfrb(P4DS, P4DS_);
#define P4SEL_ __MSP430_PORT4_BASE__ + 0x0B /* Port 4 Selection */
sfrb(P4SEL, P4SEL_);
#endif
#if defined(__MSP430_PORT5_BASE__)
#define P5IN_ __MSP430_PORT5_BASE__ + 0x00 /* Port 5 Input */
sfrb(P5IN, P5IN_);
#define P5OUT_ __MSP430_PORT5_BASE__ + 0x02 /* Port 5 Output */
sfrb(P5OUT, P5OUT_);
#define P5DIR_ __MSP430_PORT5_BASE__ + 0x04 /* Port 5 Direction */
sfrb(P5DIR, P5DIR_);
#define P5REN_ __MSP430_PORT5_BASE__ + 0x06 /* Port 5 Resistor enable */
sfrb(P5REN, P5REN_);
#define P5DS_ __MSP430_PORT5_BASE__ + 0x08 /* Port 5 Drive strength */
sfrb(P5DS, P5DS_);
#define P5SEL_ __MSP430_PORT5_BASE__ + 0x0A /* Port 5 Selection */
sfrb(P5SEL, P5SEL_);
#endif
#if defined(__MSP430_PORT6_BASE__)
#define P6IN_ __MSP430_PORT6_BASE__ + 0x01 /* Port 6 Input */
sfrb(P6IN, P6IN_);
#define P6OUT_ __MSP430_PORT6_BASE__ + 0x03 /* Port 6 Output */
sfrb(P6OUT, P6OUT_);
#define P6DIR_ __MSP430_PORT6_BASE__ + 0x05 /* Port 6 Direction */
sfrb(P6DIR, P6DIR_);
#define P6REN_ __MSP430_PORT6_BASE__ + 0x07 /* Port 6 Resistor enable */
sfrb(P6REN, P6REN_);
#define P6DS_ __MSP430_PORT6_BASE__ + 0x09 /* Port 6 Drive strength */
sfrb(P6DS, P6DS_);
#define P6SEL_ __MSP430_PORT6_BASE__ + 0x0B /* Port 6 Selection */
sfrb(P6SEL, P6SEL_);
#endif
#if defined(__MSP430_PORT7_BASE__)
#define P7IN_ __MSP430_PORT7_BASE__ + 0x00 /* Port 7 Input */
sfrb(P7IN, P7IN_);
#define P7OUT_ __MSP430_PORT7_BASE__ + 0x02 /* Port 7 Output */
sfrb(P7OUT, P7OUT_);
#define P7DIR_ __MSP430_PORT7_BASE__ + 0x04 /* Port 7 Direction */
sfrb(P7DIR, P7DIR_);
#define P7REN_ __MSP430_PORT7_BASE__ + 0x06 /* Port 7 Resistor enable */
sfrb(P7REN, P7REN_);
#define P7DS_ __MSP430_PORT7_BASE__ + 0x08 /* Port 7 Drive strength */
sfrb(P7DS, P7DS_);
#define P7SEL_ __MSP430_PORT7_BASE__ + 0x0A /* Port 7 Selection */
sfrb(P7SEL, P7SEL_);
#endif
#if defined(__MSP430_PORT8_BASE__)
#define P8IN_ __MSP430_PORT8_BASE__ + 0x01 /* Port 8 Input */
sfrb(P8IN, P8IN_);
#define P8OUT_ __MSP430_PORT8_BASE__ + 0x03 /* Port 8 Output */
sfrb(P8OUT, P8OUT_);
#define P8DIR_ __MSP430_PORT8_BASE__ + 0x05 /* Port 8 Direction */
sfrb(P8DIR, P8DIR_);
#define P8REN_ __MSP430_PORT8_BASE__ + 0x07 /* Port 8 Resistor enable */
sfrb(P8REN, P8REN_);
#define P8DS_ __MSP430_PORT8_BASE__ + 0x09 /* Port 8 Drive strength */
sfrb(P8DS, P8DS_);
#define P8SEL_ __MSP430_PORT8_BASE__ + 0x0B /* Port 8 Selection */
sfrb(P8SEL, P8SEL_);
#endif
#if defined(__MSP430_PORT9_BASE__)
#define P9IN_ __MSP430_PORT9_BASE__ + 0x00 /* Port 9 Input */
sfrb(P9IN, P9IN_);
#define P9OUT_ __MSP430_PORT9_BASE__ + 0x02 /* Port 9 Output */
sfrb(P9OUT, P9OUT_);
#define P9DIR_ __MSP430_PORT9_BASE__ + 0x04 /* Port 9 Direction */
sfrb(P9DIR, P9DIR_);
#define P9REN_ __MSP430_PORT9_BASE__ + 0x06 /* Port 9 Resistor enable */
sfrb(P9REN, P9REN_);
#define P9DS_ __MSP430_PORT9_BASE__ + 0x08 /* Port 9 Drive strength */
sfrb(P9DS, P9DS_);
#define P9SEL_ __MSP430_PORT9_BASE__ + 0x0A /* Port 9 Selection */
sfrb(P9SEL, P9SEL_);
#endif
#if defined(__MSP430_PORT10_BASE__)
#define P10IN_ __MSP430_PORT10_BASE__ + 0x01 /* Port 10 Input */
sfrb(P10IN, P10IN_);
#define P10OUT_ __MSP430_PORT10_BASE__ + 0x03 /* Port 10 Output */
sfrb(P10OUT, P10OUT_);
#define P10DIR_ __MSP430_PORT10_BASE__ + 0x05 /* Port 10 Direction */
sfrb(P10DIR, P10DIR_);
#define P10REN_ __MSP430_PORT10_BASE__ + 0x07 /* Port 10 Resistor enable */
sfrb(P10REN, P10REN_);
#define P10DS_ __MSP430_PORT10_BASE__ + 0x09 /* Port 10 Drive strength */
sfrb(P10DS, P10DS_);
#define P10SEL_ __MSP430_PORT10_BASE__ + 0x0B /* Port 10 Selection */
sfrb(P10SEL, P10SEL_);
#endif
#if defined(__MSP430_PORT11_BASE__)
#define P11IN_ __MSP430_PORT11_BASE__ + 0x00 /* Port 11 Input */
sfrb(P11IN, P11IN_);
#define P11OUT_ __MSP430_PORT11_BASE__ + 0x02 /* Port 11 Output */
sfrb(P11OUT, P11OUT_);
#define P11DIR_ __MSP430_PORT11_BASE__ + 0x04 /* Port 11 Direction */
sfrb(P11DIR, P11DIR_);
#define P11REN_ __MSP430_PORT11_BASE__ + 0x06 /* Port 11 Resistor enable */
sfrb(P11REN, P11REN_);
#define P11DS_ __MSP430_PORT11_BASE__ + 0x08 /* Port 11 Drive strength */
sfrb(P11DS, P11DS_);
#define P11SEL_ __MSP430_PORT11_BASE__ + 0x0A /* Port 11 Selection */
sfrb(P11SEL, P11SEL_);
#endif
#if defined(__MSP430_PORTJ_BASE__)
#define PJIN_ __MSP430_PORTJ_BASE__ + 0x00 /* Port J Input */
sfrb(PJIN, PJIN_);
#define PJOUT_ __MSP430_PORTJ_BASE__ + 0x02 /* Port J Output */
sfrb(PJOUT, PJOUT_);
#define PJDIR_ __MSP430_PORTJ_BASE__ + 0x04 /* Port J Direction */
sfrb(PJDIR, PJDIR_);
#define PJREN_ __MSP430_PORTJ_BASE__ + 0x06 /* Port J Resistor enable */
sfrb(PJREN, PJREN_);
#define PJDS_ __MSP430_PORTJ_BASE__ + 0x08 /* Port J Drive strength */
sfrb(PJDS, PJDS_);
#endif
#endif /* __MSP430_HEADERS_GPIO5_XXX_H */
--- NEW FILE: mpy32.h ---
#ifndef __MSP430_HEADERS_MPY32_H
#define __MSP430_HEADERS_MPY32_H
/* mpy.h
*
* mspgcc project: MSP430 device headers
* Hardware 32-bit multiplier
*
* (c) 2008 by Sergey A. Borshch <sb-sf@...>
* Originally based in MSP430F543x datasheet (slas609)
* and MSP430x5xx Family User's Guide (slau208).
*
* $Id: mpy32.h,v 1.1 2008/12/07 22:45:57 sb-sf Exp $
*/
/* Switches:
__MSP430_MPY32_BASE__ - base address of MPY32 module
*/
#if defined(__MSP430_MPY32_BASE__)
#define MPY_ __MSP430_MPY32_BASE__ + 0x00 /* 16-bit operand 1 - multiply */
sfrw(MPY, MPY_);
#define MPYS_ __MSP430_MPY32_BASE__ + 0x02 /* 16-bit operand 1 - signed multiply */
sfrw(MPYS, MPYS_);
#define MAC_ __MSP430_MPY32_BASE__ + 0x04 /* 16-bit operand 1 - multiply accumulate */
sfrw(MAC, MAC_);
#define MACS_ __MSP430_MPY32_BASE__ + 0x06 /* 16-bit operand 1 - signed multiply accumulate */
sfrw(MACS, MACS_);
#define OP2_ __MSP430_MPY32_BASE__ + 0x08 /* 16-bit operand 2 */
sfrw(OP2, OP2_);
#define RESLO_ __MSP430_MPY32_BASE__ + 0x0A /* 16x16 result low word */
sfrw(RESLO, RESLO_);
#define RESHI_ __MSP430_MPY32_BASE__ + 0x0C /* 16x16 result high word */
sfrw(RESHI, RESHI_);
#define SUMEXT_ __MSP430_MPY32_BASE__ + 0x0E /* 16x16 sum extension */
sfrw(SUMEXT, SUMEXT_);
#define MPY32L_ __MSP430_MPY32_BASE__ + 0x10 /* 32-bit operand 1 - multiply low word */
sfrw(MPY32L, MPY32L_);
#define MPY32H_ __MSP430_MPY32_BASE__ + 0x12 /* 32-bit operand 1 - multiply high word */
sfrw(MPY32H, MPY32H_);
#define MPYS32L_ __MSP430_MPY32_BASE__ + 0x14 /* 32-bit operand 1 - signed multiply low word */
sfrw(MPYS32L, MPYS32L_);
#define MPYS32H_ __MSP430_MPY32_BASE__ + 0x16 /* 32-bit operand 1 - signed multiply high word */
sfrw(MPYS32H, MPYS32H_);
#define MAC32L_ __MSP430_MPY32_BASE__ + 0x18 /* 32-bit operand 1 - multiply accumulate low word */
sfrw(MAC32L, MAC32L_);
#define MAC32H_ __MSP430_MPY32_BASE__ + 0x1A /* 32-bit operand 1 - multiply accumulate high word */
sfrw(MAC32H, MAC32H_);
#define MACS32L_ __MSP430_MPY32_BASE__ + 0x1C /* 32-bit operand 1 - signed multiply accumulate low word */
sfrw(MACS32L, MACS32L_);
#define MACS32H_ __MSP430_MPY32_BASE__ + 0x1E /* 32-bit operand 1 - signed multiply accumulate high word */
sfrw(MACS32H, MACS32H_);
#define OP2L_ __MSP430_MPY32_BASE__ + 0x20 /* 32-bit operand 2 - low word */
sfrw(OP2L, OP2L_);
#define OP2H_ __MSP430_MPY32_BASE__ + 0x22 /* 32-bit operand 2 - high word */
sfrw(OP2H, OP2H_);
#define RES0_ __MSP430_MPY32_BASE__ + 0x24 /* 32x32 result 3 - least significant word */
sfrw(RES0,RES0_);
#define RES1_ __MSP430_MPY32_BASE__ + 0x26
sfrw(RES1,RES1_);
#define RES2_ __MSP430_MPY32_BASE__ + 0x28
sfrw(RES2,RES2_);
#define RES3_ __MSP430_MPY32_BASE__ + 0x2A /* 32x32 result 3 - most significant word */
sfrw(RES3,RES3_);
#define MPY32CTL0_ __MSP430_MPY32_BASE__ + 0x2C /* MPY32 control register 0 */
sfrw(MPY32CTL0,MPY32CTL0_);
#endif /* defined(__MSP430_MPY32_BASE__) */
#define MPYDLY32 (1<<9) /* Delayed write mode */
#define MPYDLYWRTEN (1<<8) /* Delayed write enable */
#define MPYPO2_32 (1<<7) /* Multiplier bit width of operand 2 */
#define MPYPO1_32 (1<<6) /* Multiplier bit width of operand 1 */
#define MPYM1 (1<<5) /* Multiplier mode */
#define MPYM0 (1<<4) /* -- // -- */
#define MPYSAT (1<<3) /* Saturation mode */
#define MPYFRAC (1<<2) /* Fractional mode */
#define MPYC (1<<0) /* Carry of the multiplier */
#define MPYM_0 (0<<4) /* Multiply */
#define MPYM_1 (1<<4) /* Signed multiply */
#define MPYM_2 (2<<4) /* Multiply accumulate */
#define MPYM_1 (3<<4) /* Signed multiply accumulate */
#ifndef __ASSEMBLER__
/* Structured declaration */
#undef __xstr
#undef __str
#define __xstr(x) __str(x)
#define __str(x) #x
#ifdef __cplusplus
extern "C"
#endif //__cplusplus
struct
{
volatile unsigned int MPY; /* 16-bit operand 1 - multiply */
volatile unsigned int MPYS; /* 16-bit operand 1 - signed multiply */
volatile unsigned int MAC; /* 16-bit operand 1 - multiply accumulate */
volatile unsigned int MACS; /* 16-bit operand 1 - signed multiply accumulate */
volatile unsigned int OP2; /* 16-bit operand 2 */
volatile unsigned int RESLO; /* 16x16 result low word */
volatile unsigned int RESHI; /* 16x16 result high word */
volatile const unsigned int SUMEXT; /* 16x16 sum extension */
volatile unsigned int MPY32L; /* 32-bit operand 1 - multiply low word */
volatile unsigned int MPY32H; /* 32-bit operand 1 - multiply high word */
volatile unsigned int MPYS32L; /* 32-bit operand 1 - signed multiply low word */
volatile unsigned int MPYS32H; /* 32-bit operand 1 - signed multiply high word */
volatile unsigned int MAC32L; /* 32-bit operand 1 - multiply accumulate low word */
volatile unsigned int MAC32H; /* 32-bit operand 1 - multiply accumulate high word */
volatile unsigned int MACS32L; /* 32-bit operand 1 - signed multiply accumulate low word */
volatile unsigned int MACS32H; /* 32-bit operand 1 - signed multiply accumulate high word */
volatile unsigned int OP2L; /* 32-bit operand 2 - low word */
volatile unsigned int OP2H; /* 32-bit operand 2 - high word */
volatile unsigned int RES0; /* 32x32 result 3 - least significant word */
volatile unsigned int RES1;
volatile unsigned int RES2;
volatile unsigned int RES3; /* 32x32 result 3 - most significant word */
volatile unsigned int MPY32CTL0; /* MPY32 control register 0 */
} mpy32 asm(__xstr(__MSP430_MPY32_BASE__));
#undef __str
#undef __xstr
#endif /* __ASSEMBLER__ */
#endif /* __MSP430_HEADERS_MPY32_H */
--- NEW FILE: sys.h ---
#ifndef __MSP430_HEADERS_SYS_H
#define __MSP430_HEADERS_SYS_H
/* sys.h
*
* mspgcc project: MSP430 device headers
* system control module
*
* (c) 2008 by Sergey A. Borshch <sb-sf@...>
* Originally based in MSP430F543x datasheet (slas609)
* and MSP430x5xx Family User's Guide (slau208).
*
* $Id: sys.h,v 1.1 2008/12/07 22:45:57 sb-sf Exp $
*/
/* Switches:
__MSP430_SYS_BASE__ - base address of SYS module
*/
#define SYSCTL_ __MSP430_SYS_BASE__ + 0x00 /* System control register */
sfrw(SYSCTL, SYSCTL_);
#define SYSCTL_L_ __MSP430_SYS_BASE__ + 0x00 /* low byte */
sfrb(SYSCTL_L, SYSCTL_L_);
#define SYSCTL_H_ __MSP430_SYS_BASE__ + 0x01 /* high byte */
sfrb(SYSCTL_H, SYSCTL_H_);
#define SYSBSLC_ __MSP430_SYS_BASE__ + 0x02 /* Bootstrap loader configuration register */
sfrw(SYSBSLC, SYSBSLC_);
#define SYSBSLC_L_ __MSP430_SYS_BASE__ + 0x02 /* low byte */
sfrb(SYSBSLC_L, SYSBSLC_L_);
#define SYSBSLC_H_ __MSP430_SYS_BASE__ + 0x03 /* high byte */
sfrb(SYSBSLC_H, SYSBSLC_H_);
#define SYSARB_ __MSP430_SYS_BASE__ + 0x04 /* Arbitration configuration register */
sfrw(SYSARB, SYSARB_);
#define SYSARB_L_ __MSP430_SYS_BASE__ + 0x04 /* low byte */
sfrb(SYSARB_L, SYSARB_L_);
#define SYSARB_H_ __MSP430_SYS_BASE__ + 0x05 /* high byte */
sfrb(SYSARB_H, SYSARB_H_);
#define SYSJMBC_ __MSP430_SYS_BASE__ + 0x06 /* JTAG Mailbox control register */
sfrw(SYSJMBC, SYSJMBC_);
#define SYSJMBC_L_ __MSP430_SYS_BASE__ + 0x06 /* low byte */
sfrb(SYSJMBC_L, SYSJMBC_L_);
#define SYSJMBC_H_ __MSP430_SYS_BASE__ + 0x07 /* high byte */
sfrb(SYSJMBC_H, SYSJMBC_H_);
#define SYSJMBI0_ __MSP430_SYS_BASE__ + 0x08 /* JTAG Mailbox input register #0 */
sfrw(SYSJMBI0, SYSJMBI0_);
#define SYSJMBI0_L_ __MSP430_SYS_BASE__ + 0x08 /* low byte */
sfrb(SYSJMBI0_L, SYSJMBI0_L_);
#define SYSJMBI0_H_ __MSP430_SYS_BASE__ + 0x09 /* high byte */
sfrb(SYSJMBI0_H, SYSJMBI0_H_);
#define SYSJMBI1_ __MSP430_SYS_BASE__ + 0x0A /* JTAG Mailbox input register #1 */
sfrw(SYSJMBI1, SYSJMBI1_);
#define SYSJMBI1_L_ __MSP430_SYS_BASE__ + 0x0A /* low byte */
sfrb(SYSJMBI1_L, SYSJMBI1_L_);
#define SYSJMBI1_H_ __MSP430_SYS_BASE__ + 0x0B /* high byte */
sfrb(SYSJMBI1_H, SYSJMBI1_H_);
#define SYSJMBO0_ __MSP430_SYS_BASE__ + 0x0C /* JTAG Mailbox output register #0 */
sfrw(SYSJMBO0, SYSJMBO0_);
#define SYSJMBO0_L_ __MSP430_SYS_BASE__ + 0x0C /* low byte */
sfrb(SYSJMBO0_L, SYSJMBO0_L_);
#define SYSJMBO0_H_ __MSP430_SYS_BASE__ + 0x0D /* high byte */
sfrb(SYSJMBO0_H, SYSJMBO0_H_);
#define SYSJMBO1_ __MSP430_SYS_BASE__ + 0x0E /* JTAG Mailbox output register #1 */
sfrw(SYSJMBO1, SYSJMBO1_);
#define SYSJMBO1_L_ __MSP430_SYS_BASE__ + 0x0E /* low byte */
sfrb(SYSJMBO1_L, SYSJMBO1_L_);
#define SYSJMBO1_H_ __MSP430_SYS_BASE__ + 0x0F /* high byte */
sfrb(SYSJMBO1_H, SYSJMBO1_H_);
#define SYSBERRIV_ __MSP430_SYS_BASE__ + 0x18 /* Bus error vector generator */
sfrw(SYSBERRIV, SYSBERRIV_);
#define SYSUNIV_ __MSP430_SYS_BASE__ + 0x1A /* User NMI vector generator */
sfrw(SYSUNIV, SYSUNIV_);
#define SYSSNIV_ __MSP430_SYS_BASE__ + 0x1C /* System NMI vector generator */
sfrw(SYSSNIV, SYSSNIV_);
#define SYSRSTIV_ __MSP430_SYS_BASE__ + 0x1E /* System reset vector generator */
sfrw(SYSRSTIV, SYSRSTIV_);
/* SYSCTL, SYSCTL_L */
#define SYSJTAGPIN (1<<5) /* Dedicated JTAG pins enable */
#define SYSBSLIND (1<<4) /* TCK/RST entry BSL indication detected */
#define SYSPMMPE (1<<2) /* PMM access protect */
#define SYSRIVECT (1<<0) /* RAM based interrupt vectors */
/* SYSBSLC, SYSBSLC_L, SYSBSLC_H */
#define SYSBSLPE (1<<15) /* BSL memory protection enable */
#define SYSBSLOFF (1<<14) /* BSL memory disable for size covered in SYSBSLSIZE */
#define SYSBSLR (1<<2) /* RAM assigned to BSL */
#define SYSBSLSIZE1 (1<<1) /* BSL size */
#define SYSBSLSIZE0 (1<<0) /* BSL size */
#define SYSBSLSIZE_0 (0<<0) /* size 512 bytes, BSL_SEG_3 */
#define SYSBSLSIZE_1 (0<<1) /* size 1024 bytes, BSL_SEG_2,3 */
#define SYSBSLSIZE_2 (0<<2) /* size 1536 bytes, BSL_SEG_1,2,3 */
#define SYSBSLSIZE_3 (0<<3) /* size 2048 bytes, BSL_SEG_0,1,2,3 */
/* SYSJMBC, SYSJMBC_L */
#define JMBCLR1OFF (1<<7) /* Incomming JTAG mailbox 1 flag auto-clear disable */
#define MBCLR0OFF (1<<6) /* Incomming JTAG mailbox 0 flag auto-clear disable */
#define JMBMODE (1<<4) /* Operation mode of JMB for JMBI0/1 and JMBO0/1 */
#define JMBOUT1FG (1<<3) /* Outgoing JTAG mailbox 1 flag */
#define JMBOUT0FG (1<<2) /* Outgoing JTAG mailbox 0 flag */
#define JMBIN1FG (1<<1) /* Incoming JTAG mailbox 1 flag */
#define JMBIN0FG (1<<0) /* Incoming JTAG mailbox 0 flag */
#ifndef __ASSEMBLER__
/* Structured declaration */
#undef __xstr
#undef __str
#define __xstr(x) __str(x)
#define __str(x) #x
#ifdef __cplusplus
extern "C"
#endif //__cplusplus
typedef struct
{
union
{
volatile unsigned int CTL; /* System control register */
struct
{
volatile unsigned char CTL_L; /* low byte */
volatile unsigned char CTL_H; /* high byte */
};
};
union
{
volatile unsigned int BSLC; /* Bootstrap loader configuration register */
struct
{
volatile unsigned char BSLC_L; /* low byte */
volatile unsigned char BSLC_H; /* high byte */
};
};
union
{
volatile unsigned int ARB; /* Arbitration configuration register */
struct
{
volatile unsigned char ARB_L; /* low byte */
volatile unsigned char ARB_H; /* high byte */
};
};
union
{
volatile unsigned int JMBC; /* JTAG Mailbox control register */
struct
{
volatile unsigned char JMBC_L; /* low byte */
volatile unsigned char JMBC_H; /* high byte */
};
};
union
{
volatile unsigned int JMBI0; /* JTAG Mailbox input register #0 */
struct
{
volatile unsigned char JMBI0_L; /* low byte */
volatile unsigned char JMBI0_H; /* high byte */
};
};
union
{
volatile unsigned int JMBI1; /* JTAG Mailbox input register #1 */
struct
{
volatile unsigned char JMBI1_L; /* low byte */
volatile unsigned char JMBI1_H; /* high byte */
};
};
union
{
volatile unsigned int JMBO0; /* JTAG Mailbox output register #0 */
struct
{
volatile unsigned char JMBO0_L; /* low byte */
volatile unsigned char JMBO0_H; /* high byte */
};
};
union
{
volatile unsigned int JMBO1; /* JTAG Mailbox output register #1 */
struct
{
volatile unsigned char JMBO1_L; /* low byte */
volatile unsigned char JMBO1_H; /* high byte */
};
};
unsigned int dummy[4];
volatile unsigned int BERRIV; /* Bus error vector generator */
volatile unsigned int UNIV; /* User NMI vector generator */
volatile unsigned int SNIV; /* System NMI vector generator */
volatile unsigned int RSTIV; /* System reset vector generator */
} sys_t;
sys_t SYS asm(__xstr(__MSP430_SYS_BASE__));
#endif /* __ASSEMBLER__ */
#endif /* __MSP430_HEADERS_SYS_H */
--- NEW FILE: wdt_a.h ---
#ifndef __MSP430_HEADERS_WDT_A_H
#define __MSP430_HEADERS_WDT_A_H
/* wdt_a.h
*
* mspgcc project: MSP430 device headers
* watchdog timer module
*
* (c) 2008 by Sergey A. Borshch <sb-sf@...>
* Originally based in MSP430F543x datasheet (slas609)
* and MSP430x5xx Family User's Guide (slau208).
*
* $Id: wdt_a.h,v 1.1 2008/12/07 22:45:57 sb-sf Exp $
*/
/* Switches:
__MSP430_WDT_A_BASE__ - base address of WDT_A module
*/
#define WDTCTL_ __MSP430_WDT_A_BASE__ + 0x00 /* Watchdog timer control register */
sfrw(WDTCTL, WDTCTL_);
/* WDTCTL */
#define WDTPW (0xA5<<8) /* Watchdog timer password. Always read as 069h. Must be written as 05Ah, or a PUC will be generated */
#define WDTHOLD (1<<7) /* Watchdog timer hold */
#define WDTSSEL1 (1<<6) /* Watchdog timer clock source select */
#define WDTSSEL0 (1<<5) /* Watchdog timer clock source select */
#define WDTTMSEL (1<<4) /* Watchdog timer mode select */
#define WDTCNTCL (1<<3) /* Watchdog timer counter clear */
#define WDTIS2 (1<<2) /* Watchdog timer interval select */
#define WDTIS1 (1<<1) /* Watchdog timer interval select */
#define WDTIS0 (1<<0) /* Watchdog timer interval select */
/* Aliases by mspgcc */
#define WDTIS_0 (0<<0) /* Watchdog timer /64 */
#define WDTIS_1 (1<<0) /* Watchdog timer /512 */
#define WDTIS_2 (2<<0) /* Watchdog timer /8192 */
#define WDTIS_3 (3<<0) /* Watchdog timer /32K */
#define WDTIS_4 (4<<0) /* Watchdog timer /512K */
#define WDTIS_5 (5<<0) /* Watchdog timer /8192K */
#define WDTIS_6 (6<<0) /* Watchdog timer /128M */
#define WDTIS_7 (7<<0) /* Watchdog timer /2G */
#define WDTSSEL_0 (0<<5) /* Watchdog clock SMCLK */
#define WDTSSEL_0 (1<<5) /* Watchdog clock ACLK */
#define WDTSSEL_0 (2<<5) /* Watchdog clock VLOCLK */
#define WDTSSEL_0 (3<<5) /* Watchdog clock X_CLK */
/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fMCLK (assumed 1MHz) */
#define WDT_SMDLY_2147S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_0) /* 2147s */
#define WDT_SMDLY_134S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_1) /* 134s */
#define WDT_SMDLY_8S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_2) /* 8.38s */
#define WDT_SMDLY_500MS (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_3) /* 524ms */
#define WDT_SMDLY_32 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_4) /* 32ms interval (default) */
#define WDT_SMDLY_8 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_5) /* 8ms */
#define WDT_SMDLY_0_5 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_6) /* 0.5ms */
#define WDT_SMDLY_0_064 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_0|WDTIS_7) /* 0.064ms */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_65536S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_0) /* 65536s */
#define WDT_ADLY_4096S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_1) /* 4096s */
#define WDT_ADLY_256S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_2) /* 256s */
#define WDT_ADLY_16S (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_3) /* 16s */
#define WDT_ADLY_1000 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_4) /* 1000ms */
#define WDT_ADLY_250 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_5) /* 250ms */
#define WDT_ADLY_16 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_6) /* 16ms */
#define WDT_ADLY_1_9 (WDTPW|WDTTMSEL|WDTCNTCL|WDTSSEL_1|WDTIS_7) /* 1.9ms */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_SMRST_2147S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_0) /* 2147s */
#define WDT_SMRST_134S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_1) /* 134s */
#define WDT_SMRST_8S (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_2) /* 8.38s */
#define WDT_SMRST_500MS (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_3) /* 524ms */
#define WDT_SMRST_32 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_4) /* 32ms interval (default) */
#define WDT_SMRST_8 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_5) /* 8ms */
#define WDT_SMRST_0_5 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_6) /* 0.5ms */
#define WDT_SMRST_0_064 (WDTPW|WDTCNTCL|WDTSSEL_0|WDTIS_7) /* 0.064ms */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ARST_65536S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_0) /* 65536s */
#define WDT_ARST_4096S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_1) /* 4096s */
#define WDT_ARST_256S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_2) /* 256s */
#define WDT_ARST_16S (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_3) /* 16s */
#define WDT_ARST_1000 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_4) /* 1s */
#define WDT_ARST_250 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_5) /* 250ms */
#define WDT_ARST_16 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_6) /* 16ms */
#define WDT_ARST_1_9 (WDTPW|WDTCNTCL|WDTSSEL_1|WDTIS_7) /* 1.9ms */
#ifndef __ASSEMBLER__
/* Structured declaration */
#undef __xstr
#undef __str
#define __xstr(x) __str(x)
#define __str(x) #x
#ifdef __cplusplus
extern "C"
#endif //__cplusplus
volatile unsigned int WDTCTL asm(__xstr(__MSP430_WDT_A_BASE__)); /* Watchdog timer control register */
#endif /* __ASSEMBLER__ */
#endif /* __MSP430_HEADERS_SYS_H */
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