Update of /cvsroot/linuxsh/linux/arch/sh/drivers/pci
In directory sc8-pr-cvs1:/tmp/cvs-serv16516/arch/sh/drivers/pci
Modified Files:
Makefile pci-sh7751.c
Added Files:
ops-bigsur.c ops-snapgear.c pci-sh7751.h
Log Message:
New SH7751 PCI interface.
--- NEW FILE: ops-bigsur.c ---
/*
* linux/arch/sh/kernel/pci-bigsur.c
*
* By Dustin McIntire (dustin@...) (c)2001
*
* Ported to new API by Paul Mundt <lethal@...>.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* PCI initialization for the Hitachi Big Sur Evaluation Board
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/io.h>
#include "pci-sh7751.h"
#include <asm/bigsur/bigsur.h>
#define BIGSUR_PCI_IO 0x4000
#define BIGSUR_PCI_MEM 0xfd000000
static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = BIGSUR_PCI_IO,
.end = BIGSUR_PCI_IO + (64*1024) - 1,
.flags = IORESOURCE_IO,
};
static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = BIGSUR_PCI_MEM,
.end = BIGSUR_PCI_MEM + (64*1024*1024) - 1,
.flags = IORESOURCE_MEM,
};
extern struct pci_ops sh7751_pci_ops;
struct pci_channel board_pci_channels[] = {
{ &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ 0, }
};
static struct sh7751_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS3_BASE_ADDR,
.size = BIGSUR_LSR0_SIZE,
},
.window1 = {
.base = SH7751_CS3_BASE_ADDR,
.size = BIGSUR_LSR1_SIZE,
},
};
/*
* Initialize the Big Sur PCI interface
* Setup hardware to be Central Funtion
* Copy the BSR regs to the PCI interface
* Setup PCI windows into local RAM
*/
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&sh7751_pci_map);
}
int pcibios_map_platform_irq(u8 slot, u8 pin)
{
/*
* The Big Sur can be used in a CPCI chassis, but the SH7751 PCI
* interface is on the wrong end of the board so that it can also
* support a V320 CPI interface chip... Therefor the IRQ mapping is
* somewhat use dependent... I'l assume a linear map for now, i.e.
* INTA=slot0,pin0... INTD=slot3,pin0...
*/
int irq = (slot + pin-1) % 4 + BIGSUR_SH7751_PCI_IRQ_BASE;
PCIDBG(2, "PCI: Mapping Big Sur IRQ for slot %d, pin %c to irq %d\n",
slot, pin-1+'A', irq);
return irq;
}
--- NEW FILE: ops-snapgear.c ---
/*
* arch/sh/drivers/pci/ops-snapgear.c
*
* Author: David McCullough <davidm@...>
*
* Ported to new API by Paul Mundt <lethal@...>
*
* Highly leveraged from pci-bigsur.c, written by Dustin McIntire.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* PCI initialization for the SnapGear boards
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <asm/io.h>
#include "pci-sh7751.h"
#define SNAPGEAR_PCI_IO 0x4000
#define SNAPGEAR_PCI_MEM 0xfd000000
/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
#define SNAPGEAR_LSR0_SIZE (64*(1<<20)) //64MB
#define SNAPGEAR_LSR1_SIZE (64*(1<<20)) //64MB
static struct resource sh7751_io_resource = {
.name = "SH7751 IO",
.start = SNAPGEAR_PCI_IO,
.end = SNAPGEAR_PCI_IO + (64*1024) - 1, /* 64KiB I/O */
.flags = IORESOURCE_IO,
};
static struct resource sh7751_mem_resource = {
.name = "SH7751 mem",
.start = SNAPGEAR_PCI_MEM,
.end = SNAPGEAR_PCI_MEM + (64*1024*1024) - 1, /* 64MiB mem */
.flags = IORESOURCE_MEM,
};
extern struct pci_ops sh7751_pci_ops;
struct pci_channel board_pci_channels[] = {
{ &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff },
{ 0, }
};
static struct sh7751_pci_address_map sh7751_pci_map = {
.window0 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SNAPGEAR_LSR0_SIZE,
},
.window1 = {
.base = SH7751_CS2_BASE_ADDR,
.size = SNAPGEAR_LSR1_SIZE,
},
};
/*
* Initialize the SnapGear PCI interface
* Setup hardware to be Central Funtion
* Copy the BSR regs to the PCI interface
* Setup PCI windows into local RAM
*/
int __init pcibios_init_platform(void)
{
return sh7751_pcic_init(&sh7751_pci_map);
}
int __init pcibios_map_platform_irq(u8 slot, u8 pin)
{
int irq = -1;
switch (slot) {
case 8: /* the PCI bridge */ break;
case 11: irq = 8; break; /* USB */
case 12: irq = 11; break; /* PCMCIA */
case 13: irq = 5; break; /* eth0 */
case 14: irq = 8; break; /* eth1 */
case 15: irq = 11; break; /* safenet (unused) */
}
printk("PCI: Mapping SnapGear IRQ for slot %d, pin %c to irq %d\n",
slot, pin - 1 + 'A', irq);
return irq;
}
void __init pcibios_fixup(void)
{
/* Nothing to fixup .. */
}
--- NEW FILE: pci-sh7751.h ---
/*
* Low-Level PCI Support for SH7751 targets
*
* Dustin McIntire (dustin@...) (c) 2001
* Paul Mundt (lethal@...) (c) 2003
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
*/
#ifndef _PCI_SH7751_H_
#define _PCI_SH7751_H_
#include <linux/pci.h>
/* set debug level 4=verbose...1=terse */
//#define DEBUG_PCI 3
#undef DEBUG_PCI
#ifdef DEBUG_PCI
#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
#else
#define PCIDBG(n, x...)
#endif
/* startup values */
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
#define PCI_NO_SORT 0x100
#define PCI_BIOS_SORT 0x200
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
/* Platform Specific Values */
#define SH7751_VENDOR_ID 0x1054
#define SH7751_DEVICE_ID 0x3505
#define SH7751R_DEVICE_ID 0x350e
/* SH7751 Specific Values */
#define SH7751_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
#define SH7751_PCI_CONFIG_SIZE 0x1000000 /* Config space size */
#define SH7751_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
#define SH7751_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
#define SH7751_PCI_IO_BASE 0xFE240000 /* IO space base address */
#define SH7751_PCI_IO_SIZE 0x40000 /* Size of IO window */
#define SH7751_PCIREG_BASE 0xFE200000 /* PCI regs base address */
#define PCI_REG(n) (SH7751_PCIREG_BASE+ n)
#define SH7751_PCICONF0 0x0 /* PCI Config Reg 0 */
#define SH7751_PCICONF0_DEVID 0xFFFF0000 /* Device ID */
#define SH7751_PCICONF0_VNDID 0x0000FFFF /* Vendor ID */
#define SH7751_PCICONF1 0x4 /* PCI Config Reg 1 */
#define SH7751_PCICONF1_DPE 0x80000000 /* Data Parity Error */
#define SH7751_PCICONF1_SSE 0x40000000 /* System Error Status */
#define SH7751_PCICONF1_RMA 0x20000000 /* Master Abort */
#define SH7751_PCICONF1_RTA 0x10000000 /* Target Abort Rx Status */
#define SH7751_PCICONF1_STA 0x08000000 /* Target Abort Exec Status */
#define SH7751_PCICONF1_DEV 0x06000000 /* Timing Status */
#define SH7751_PCICONF1_DPD 0x01000000 /* Data Parity Status */
#define SH7751_PCICONF1_FBBC 0x00800000 /* Back 2 Back Status */
#define SH7751_PCICONF1_UDF 0x00400000 /* User Defined Status */
#define SH7751_PCICONF1_66M 0x00200000 /* 66Mhz Operation Status */
#define SH7751_PCICONF1_PM 0x00100000 /* Power Management Status */
#define SH7751_PCICONF1_PBBE 0x00000200 /* Back 2 Back Control */
#define SH7751_PCICONF1_SER 0x00000100 /* SERR Output Control */
#define SH7751_PCICONF1_WCC 0x00000080 /* Wait Cycle Control */
#define SH7751_PCICONF1_PER 0x00000040 /* Parity Error Response */
#define SH7751_PCICONF1_VPS 0x00000020 /* VGA Pallet Snoop */
#define SH7751_PCICONF1_MWIE 0x00000010 /* Memory Write+Invalidate */
#define SH7751_PCICONF1_SPC 0x00000008 /* Special Cycle Control */
#define SH7751_PCICONF1_BUM 0x00000004 /* Bus Master Control */
#define SH7751_PCICONF1_MES 0x00000002 /* Memory Space Control */
#define SH7751_PCICONF1_IOS 0x00000001 /* I/O Space Control */
#define SH7751_PCICONF2 0x8 /* PCI Config Reg 2 */
#define SH7751_PCICONF2_BCC 0xFF000000 /* Base Class Code */
#define SH7751_PCICONF2_SCC 0x00FF0000 /* Sub-Class Code */
#define SH7751_PCICONF2_RLPI 0x0000FF00 /* Programming Interface */
#define SH7751_PCICONF2_REV 0x000000FF /* Revision ID */
#define SH7751_PCICONF3 0xC /* PCI Config Reg 3 */
#define SH7751_PCICONF3_BIST7 0x80000000 /* Bist Supported */
#define SH7751_PCICONF3_BIST6 0x40000000 /* Bist Executing */
#define SH7751_PCICONF3_BIST3_0 0x0F000000 /* Bist Passed */
#define SH7751_PCICONF3_HD7 0x00800000 /* Single Funtion device */
#define SH7751_PCICONF3_HD6_0 0x007F0000 /* Configuration Layout */
#define SH7751_PCICONF3_LAT 0x0000FF00 /* Latency Timer */
#define SH7751_PCICONF3_CLS 0x000000FF /* Cache Line Size */
#define SH7751_PCICONF4 0x10 /* PCI Config Reg 4 */
#define SH7751_PCICONF4_BASE 0xFFFFFFFC /* I/O Space Base Addr */
#define SH7751_PCICONF4_ASI 0x00000001 /* Address Space Type */
#define SH7751_PCICONF5 0x14 /* PCI Config Reg 5 */
#define SH7751_PCICONF5_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
#define SH7751_PCICONF5_LAP 0x00000008 /* Prefetch Enabled */
#define SH7751_PCICONF5_LAT 0x00000006 /* Local Memory type */
#define SH7751_PCICONF5_ASI 0x00000001 /* Address Space Type */
#define SH7751_PCICONF6 0x18 /* PCI Config Reg 6 */
#define SH7751_PCICONF6_BASE 0xFFFFFFF0 /* Mem Space Base Addr */
#define SH7751_PCICONF6_LAP 0x00000008 /* Prefetch Enabled */
#define SH7751_PCICONF6_LAT 0x00000006 /* Local Memory type */
#define SH7751_PCICONF6_ASI 0x00000001 /* Address Space Type */
/* PCICONF7 - PCICONF10 are undefined */
#define SH7751_PCICONF11 0x2C /* PCI Config Reg 11 */
#define SH7751_PCICONF11_SSID 0xFFFF0000 /* Subsystem ID */
#define SH7751_PCICONF11_SVID 0x0000FFFF /* Subsystem Vendor ID */
/* PCICONF12 is undefined */
#define SH7751_PCICONF13 0x34 /* PCI Config Reg 13 */
#define SH7751_PCICONF13_CPTR 0x000000FF /* PM function pointer */
/* PCICONF14 is undefined */
#define SH7751_PCICONF15 0x3C /* PCI Config Reg 15 */
#define SH7751_PCICONF15_IPIN 0x000000FF /* Interrupt Pin */
#define SH7751_PCICONF16 0x40 /* PCI Config Reg 16 */
#define SH7751_PCICONF16_PMES 0xF8000000 /* PME Support */
#define SH7751_PCICONF16_D2S 0x04000000 /* D2 Support */
#define SH7751_PCICONF16_D1S 0x02000000 /* D1 Support */
#define SH7751_PCICONF16_DSI 0x00200000 /* Bit Device Init. */
#define SH7751_PCICONF16_PMCK 0x00080000 /* Clock for PME req. */
#define SH7751_PCICONF16_VER 0x00070000 /* PM Version */
#define SH7751_PCICONF16_NIP 0x0000FF00 /* Next Item Pointer */
#define SH7751_PCICONF16_CID 0x000000FF /* Capability Identifier */
#define SH7751_PCICONF17 0x44 /* PCI Config Reg 17 */
#define SH7751_PCICONF17_DATA 0xFF000000 /* Data field for PM */
#define SH7751_PCICONF17_PMES 0x00800000 /* PME Status */
#define SH7751_PCICONF17_DSCL 0x00600000 /* Data Scaling Value */
#define SH7751_PCICONF17_DSEL 0x001E0000 /* Data Select */
#define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */
#define SH7751_PCICONF17_PWST 0x00000003 /* Power State */
/* SH7715 Internal PCI Registers */
#define SH7751_PCICR 0x100 /* PCI Control Register */
#define SH7751_PCICR_PREFIX 0xA5000000 /* CR prefix for write */
#define SH7751_PCICR_TRSB 0x00000200 /* Target Read Single */
#define SH7751_PCICR_BSWP 0x00000100 /* Target Byte Swap */
#define SH7751_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */
#define SH7751_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */
#define SH7751_PCICR_MD 0x00000030 /* MD9 and MD10 status */
#define SH7751_PCICR_SERR 0x00000008 /* SERR output assert */
#define SH7751_PCICR_INTA 0x00000004 /* INTA output assert */
#define SH7751_PCICR_PRST 0x00000002 /* PCI Reset Assert */
#define SH7751_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */
#define SH7751_PCILSR0 0x104 /* PCI Local Space Register0 */
#define SH7751_PCILSR1 0x108 /* PCI Local Space Register1 */
#define SH7751_PCILAR0 0x10C /* PCI Local Address Register1 */
#define SH7751_PCILAR1 0x110 /* PCI Local Address Register1 */
#define SH7751_PCIINT 0x114 /* PCI Interrupt Register */
#define SH7751_PCIINT_MLCK 0x00008000 /* Master Lock Error */
#define SH7751_PCIINT_TABT 0x00004000 /* Target Abort Error */
#define SH7751_PCIINT_TRET 0x00000200 /* Target Retry Error */
#define SH7751_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */
#define SH7751_PCIINT_PRTY 0x00000080 /* Address Parity Error */
#define SH7751_PCIINT_SERR 0x00000040 /* SERR Detection Error */
#define SH7751_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */
#define SH7751_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Error Det. */
#define SH7751_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */
#define SH7751_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */
#define SH7751_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */
#define SH7751_PCIINT_MRPD 0x00000002 /* Master Read PERR Detect */
#define SH7751_PCIINTM 0x118 /* PCI Interrupt Mask Register */
#define SH7751_PCIALR 0x11C /* Error Address Register */
#define SH7751_PCICLR 0x120 /* Error Command/Data Register */
#define SH7751_PCICLR_MPIO 0x80000000 /* Error Command/Data Register */
#define SH7751_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */
#define SH7751_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */
#define SH7751_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */
#define SH7751_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */
#define SH7751_PCICLR_TGT 0x04000000 /* Target Transfer Error */
#define SH7751_PCICLR_CMDL 0x0000000F /* PCI Command at Error */
#define SH7751_PCIAINT 0x130 /* Arbiter Interrupt Register */
#define SH7751_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */
#define SH7751_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */
#define SH7751_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */
#define SH7751_PCIAINT_TABT 0x00000008 /* Target Abort */
#define SH7751_PCIAINT_MABT 0x00000004 /* Master Abort */
#define SH7751_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */
#define SH7751_PCIAINT_WDPE 0x00000002 /* Write Data Parity Error */
#define SH7751_PCIAINTM 0x134 /* Arbiter Int. Mask Register */
#define SH7751_PCIBMLR 0x138 /* Error Bus Master Register */
#define SH7751_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */
#define SH7751_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */
#define SH7751_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */
#define SH7751_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */
#define SH7751_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */
#define SH7751_PCIDMABT 0x140 /* DMA Transfer Arb. Register */
#define SH7751_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */
#define SH7751_PCIDPA0 0x180 /* DMA0 Transfer Addr. Register */
#define SH7751_PCIDLA0 0x184 /* DMA0 Local Addr. Register */
#define SH7751_PCIDTC0 0x188 /* DMA0 Transfer Cnt. Register */
#define SH7751_PCIDCR0 0x18C /* DMA0 Control Register */
#define SH7751_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */
#define SH7751_PCIDCR_MAST 0x00000100 /* DMA Termination Type */
#define SH7751_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/
#define SH7751_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */
#define SH7751_PCIDCR_LHLD 0x00000020 /* Local Address Control */
#define SH7751_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/
#define SH7751_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */
#define SH7751_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */
#define SH7751_PCIDCR_STOP 0x00000002 /* Force DMA Stop */
#define SH7751_PCIDCR_STRT 0x00000001 /* DMA Start */
#define SH7751_PCIDPA1 0x190 /* DMA1 Transfer Addr. Register */
#define SH7751_PCIDLA1 0x194 /* DMA1 Local Addr. Register */
#define SH7751_PCIDTC1 0x198 /* DMA1 Transfer Cnt. Register */
#define SH7751_PCIDCR1 0x19C /* DMA1 Control Register */
#define SH7751_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. Register */
#define SH7751_PCIDLA2 0x1A4 /* DMA2 Local Addr. Register */
#define SH7751_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. Register */
#define SH7751_PCIDCR2 0x1AC /* DMA2 Control Register */
#define SH7751_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. Register */
#define SH7751_PCIDLA3 0x1B4 /* DMA3 Local Addr. Register */
#define SH7751_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. Register */
#define SH7751_PCIDCR3 0x1BC /* DMA3 Control Register */
#define SH7751_PCIPAR 0x1C0 /* PIO Address Register */
#define SH7751_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */
#define SH7751_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */
#define SH7751_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */
#define SH7751_PCIPAR_REGAD 0x000000FC /* Register Address Number */
#define SH7751_PCIMBR 0x1C4 /* Memory Base Address Register */
#define SH7751_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */
#define SH7751_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */
#define SH7751_PCIIOBR 0x1C8 /* I/O Base Address Register */
#define SH7751_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */
#define SH7751_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */
#define SH7751_PCIPINT 0x1CC /* Power Mgmnt Int. Register */
#define SH7751_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */
#define SH7751_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */
#define SH7751_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */
#define SH7751_PCICLKR 0x1D4 /* Clock Ctrl. Register */
#define SH7751_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */
#define SH7751_PCICLKR_BCSTP 0x00000002 /* BCLK Clock Stop */
/* For definitions of BCR, MCR see ... */
#define SH7751_PCIBCR1 0x1E0 /* Memory BCR1 Register */
#define SH7751_PCIBCR2 0x1E4 /* Memory BCR2 Register */
#define SH7751_PCIWCR1 0x1E8 /* Wait Control 1 Register */
#define SH7751_PCIWCR2 0x1EC /* Wait Control 2 Register */
#define SH7751_PCIWCR3 0x1F0 /* Wait Control 3 Register */
#define SH7751_PCIMCR 0x1F4 /* Memory Control Register */
#define SH7751_PCIPCTR 0x200 /* Port Control Register */
#define SH7751_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */
#define SH7751_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */
#define SH7751_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */
#define SH7751_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */
#define SH7751_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */
#define SH7751_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */
#define SH7751_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */
#define SH7751_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */
#define SH7751_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */
#define SH7751_PCIPDTR 0x204 /* Port Data Register */
#define SH7751_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */
#define SH7751_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */
#define SH7751_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */
#define SH7751_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */
#define SH7751_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */
#define SH7751_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */
#define SH7751_PCIPDR 0x220 /* Port IO Data Register */
/* Memory Control Registers */
#define SH7751_BCR1 0xFF800000 /* Memory BCR1 Register */
#define SH7751_BCR2 0xFF800004 /* Memory BCR2 Register */
#define SH7751_WCR1 0xFF800008 /* Wait Control 1 Register */
#define SH7751_WCR2 0xFF80000C /* Wait Control 2 Register */
#define SH7751_WCR3 0xFF800010 /* Wait Control 3 Register */
#define SH7751_MCR 0xFF800014 /* Memory Control Register */
/* General Memory Config Addresses */
#define SH7751_CS0_BASE_ADDR 0x0
#define SH7751_MEM_REGION_SIZE 0x04000000
#define SH7751_CS1_BASE_ADDR (SH7751_CS0_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS2_BASE_ADDR (SH7751_CS1_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS3_BASE_ADDR (SH7751_CS2_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS4_BASE_ADDR (SH7751_CS3_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE)
#define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE)
/* General PCI values */
#define SH7751_PCI_HOST_BRIDGE 0x6
/* External functions defined per platform i.e. Big Sur, SE... (these could be routed
* through the machine vectors... */
extern int pcibios_init_platform(void);
extern int pcibios_map_platform_irq(u8 slot, u8 pin);
struct sh7751_pci_address_space {
unsigned long base;
unsigned long size;
};
struct sh7751_pci_address_map {
struct sh7751_pci_address_space window0;
struct sh7751_pci_address_space window1;
};
/* arch/sh/drivers/pci/pci-sh7751.c */
extern int sh7751_pcic_init(struct sh7751_pci_address_map *map);
#endif /* _PCI_SH7751_H_ */
Index: Makefile
===================================================================
RCS file: /cvsroot/linuxsh/linux/arch/sh/drivers/pci/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -d -r1.1 -r1.2
--- Makefile 24 Aug 2003 19:15:45 -0000 1.1
+++ Makefile 21 Sep 2003 18:22:13 -0000 1.2
@@ -11,4 +11,6 @@
obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \
dma-dreamcast.o
+obj-$(CONFIG_SH_SECUREEDGE5410) += ops-snapgear.o
+obj-$(CONFIG_SH_BIGSUR) += ops-bigsur.o
Index: pci-sh7751.c
===================================================================
RCS file: /cvsroot/linuxsh/linux/arch/sh/drivers/pci/pci-sh7751.c,v
retrieving revision 1.2
retrieving revision 1.3
diff -u -d -r1.2 -r1.3
--- pci-sh7751.c 18 Sep 2003 02:30:06 -0000 1.2
+++ pci-sh7751.c 21 Sep 2003 18:22:13 -0000 1.3
@@ -29,7 +29,7 @@
#include <asm/io.h>
#include <asm/pci-sh7751.h>
-unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1;
+static unsigned int pci_probe = PCI_PROBE_CONF1;
/*
* Direct access to PCI hardware...
@@ -218,18 +218,166 @@
subsys_initcall(sh7751_pci_init);
+static int __init __area_sdram_check(unsigned int area)
+{
+ u32 word;
+
+ word = inl(SH7751_BCR1);
+ /* check BCR for SDRAM in area */
+ if(((word >> area) & 1) == 0) {
+ printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
+ area, word);
+ return 0;
+ }
+ outl(word, PCI_REG(SH7751_PCIBCR1));
+
+ word = (u16)inw(SH7751_BCR2);
+ /* check BCR2 for 32bit SDRAM interface*/
+ if(((word >> (area << 1)) & 0x3) != 0x3) {
+ printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
+ area, word);
+ return 0;
+ }
+ outl(word, PCI_REG(SH7751_PCIBCR2));
+
+ return 1;
+}
+
+int __init sh7751_pcic_init(struct sh7751_pci_address_map *map)
+{
+ u32 reg;
+ u32 word;
+
+ /* Set the BCR's to enable PCI access */
+ reg = inl(SH7751_BCR1);
+ reg |= 0x80000;
+ outl(reg, SH7751_BCR1);
+
+ /* Turn the clocks back on (not done in reset)*/
+ outl(0, PCI_REG(SH7751_PCICLKR));
+ /* Clear Powerdown IRQ's (not done in reset) */
+ word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0;
+ outl(word, PCI_REG(SH7751_PCICLKR));
+
+ /*
+ * XXX: This code is unused for the SnapGear boards as it is done in
+ * the bootloader and doing it here means the MAC addresses loaded by
+ * the bootloader get lost.
+ */
+#ifndef CONFIG_SH_SECUREEDGE5410
+ /* toggle PCI reset pin */
+ word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST;
+ outl(word,PCI_REG(SH7751_PCICR));
+ /* Wait for a long time... not 1 sec. but long enough */
+ mdelay(100);
+ word = SH7751_PCICR_PREFIX;
+ outl(word,PCI_REG(SH7751_PCICR));
+#endif
+
+ /* set the command/status bits to:
+ * Wait Cycle Control + Parity Enable + Bus Master +
+ * Mem space enable
+ */
+ word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
+ SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
+ outl(word, PCI_REG(SH7751_PCICONF1));
+
+ /* define this host as the host bridge */
+ word = SH7751_PCI_HOST_BRIDGE << 24;
+ outl(word, PCI_REG(SH7751_PCICONF2));
+
+ /* Set IO and Mem windows to local address
+ * Make PCI and local address the same for easy 1 to 1 mapping
+ * Window0 = map->window0.size @ non-cached area base = SDRAM
+ * Window1 = map->window1.size @ cached area base = SDRAM
+ */
+ word = map->window0.size - 1;
+ outl(word, PCI_REG(SH7751_PCILSR0));
+ word = map->window1.size - 1;
+ outl(word, PCI_REG(SH7751_PCILSR1));
+ /* Set the values on window 0 PCI config registers */
+ word = P2SEGADDR(map->window0.base);
+ outl(word, PCI_REG(SH7751_PCILAR0));
+ outl(word, PCI_REG(SH7751_PCICONF5));
+ /* Set the values on window 1 PCI config registers */
+ word = PHYSADDR(map->window1.base);
+ outl(word, PCI_REG(SH7751_PCILAR1));
+ outl(word, PCI_REG(SH7751_PCICONF6));
+
+ /* Set the local 16MB PCI memory space window to
+ * the lowest PCI mapped address
+ */
+ word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK;
+ PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word);
+ outl(word , PCI_REG(SH7751_PCIMBR));
+
+ /* Map IO space into PCI IO window
+ * The IO window is 64K-PCIBIOS_MIN_IO in size
+ * IO addresses will be translated to the
+ * PCI IO window base address
+ */
+ PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
+ (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO);
+
+ /*
+ * XXX: For now, leave this board-specific. In the event we have other
+ * boards that need to do similar work, this can be wrapped.
+ */
+#ifdef CONFIG_SH_BIGSUR
+ bigsur_port_map(PCIBIOS_MIN_IO, (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO,0);
+#endif
+
+ /* Make sure the MSB's of IO window are set to access PCI space correctly */
+ word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK;
+ PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word);
+ outl(word, PCI_REG(SH7751_PCIIOBR));
+
+ /* Set PCI WCRx, BCRx's, copy from BSC locations */
+
+ /* check BCR for SDRAM in specified area */
+ switch (map->window0.base) {
+ case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
+ case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
+ case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
+ case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
+ case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
+ case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
+ case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
+ }
+
+ if (!word)
+ return 0;
+
+ /* configure the wait control registers */
+ word = inl(SH7751_WCR1);
+ outl(word, PCI_REG(SH7751_PCIWCR1));
+ word = inl(SH7751_WCR2);
+ outl(word, PCI_REG(SH7751_PCIWCR2));
+ word = inl(SH7751_WCR3);
+ outl(word, PCI_REG(SH7751_PCIWCR3));
+ word = inl(SH7751_MCR);
+ outl(word, PCI_REG(SH7751_PCIMCR));
+
+ /* NOTE: I'm ignoring the PCI error IRQs for now..
+ * TODO: add support for the internal error interrupts and
+ * DMA interrupts...
+ */
+
+ /* SH7751 init done, set central function init complete */
+ /* use round robin mode to stop a device starving/overruning */
+ word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM;
+ outl(word,PCI_REG(SH7751_PCICR));
+
+ return 1;
+}
+
char * __init pcibios_setup(char *str)
{
if (!strcmp(str, "off")) {
pci_probe = 0;
return NULL;
- } else if (!strcmp(str, "conf1")) {
- pci_probe = PCI_PROBE_CONF1 | PCI_NO_CHECKS;
- return NULL;
- } else if (!strcmp(str, "rom")) {
- pci_probe |= PCI_ASSIGN_ROMS;
- return NULL;
}
+
return str;
}
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