El Miércoles 01 Agosto 2001 01:17, Frank C. Earl escribió:
> On Friday 27 July 2001 17:12, Manuel Teira wrote:
> > I've been checking the code performing the mapping, and I think it's all
> > right:
> > The mapping is set in atidri.c (around line 644):
> > drmAddMap( pATI->drmFD, pATI->Block1Base,
> > pATIDRIServer->regsSize,
> > DRM_REGISTERS, 0 /*DRM_READ_ONLY*/,
> > &pATIDRIServer->regsHandle );
> > pATI->Block1Base is the MMIO Block 1 address, that is calculated in
> > atipreinit.c, and correctly (I think) as in the XServer log is printed:
> Mapping addresses presumes that the part of the data you're mapping is on a
> page boundary- at least on Intel hardware that would be aligned to 4k
> boundaries because of the MMU design. So, the only time this would
> consistently work is if the driver properly found the auxillary aperture-
> any other time, it would be using the primary one, which is located such
> that block 1 is 2k from the top of the first 8Mb of the 16Mb linear
> aperture (PPC machines use the upper 8Mb for their framebuffer space,
> according to the programmer's guide.)- I was questioning the code mapping
> to the right space because of seeing the block of code in preinit that sets
> the aperture address to the primary if it can't find the auxillary one. If
> this code ever gets executed, it's going to map it all wrong.
O.K, O.K., correct me if I'm wrong. What we have here is that the MMIO
registers are mapped in two different memory places, isn't it?
And I also suppose that the mapping is wrong when using the primary aperture,
because it doesn't fit in a 4k boundary, right?
> > (II) ATI(0): Using Block 0 MMIO aperture at 0xF4200400.
> > (II) ATI(0): Using Block 1 MMIO aperture at 0xF4200000.
> > ...
> > This is concordant with the information printed by lspci on my computer:
> > ...
> > Memory at f4200000 (32-bit, non-prefetchable) [size=4K]
> > ...
> Which means your driver is finding the auxillary aperture- mine on my
> machine seems to be doing "odd" things right at the moment and not
> consistently finding it.
So, the auxiliary aperture is the one I'm using, isn't it?
> Another thing to think about is that I don't remember us ever attempting to
> do bus-mastering from the auxillary aperture; we only used the primary one
> in Utah- and the documentation could lead one to believe that you're
> supposed to do this sort of thing only with the primary aperture. So far,
> I can't see where the code would have a problem with the auxillary
> aperture, but I've only given it a cursory glance.
I'm not sure about what do you want to mean with "attempting to do bm from
the auxiliary aperture". Could we say that the only difference between doing
bm from the auxiliary aperture and the primary aperture is the mapping we
are using for the control registers?
In UTAH, the MM base is derived as:
mach64glx.MMIOBase = (char *)GLXSYM(mach64MemRegMap);
is this value the primary or the auxiliary aperture?