Thanks :) I explicitly software-enable the APIC and it works now. This i=
s
the correct behaviour, as you pointed out.
The code worked on all of my machines here so I was confused. It appears
that they all enable the local APIC before booting the system. The bochs
BIOS leaves it disabled in 2.2.6, as per the Intel documents.
Thanks again,
Durand.
----- Original Message -----=20
From: "Stanislav Shwartsman" <stl@...>
To: <clutter@...>; <bochs-developers@...>
Sent: Monday, January 30, 2006 19:39
Subject: RE: [Bochs-developers] Interrupts appear broken for SMP in 2.2.5
Read the following mail. Please fix your kernel and confirm closing of th=
e=20
bug report.
Stanislav
Bugs item #1417583, was opened at 2006-01-28 22:44 Message generated for=20
change (Comment added) made by sshwarts You can respond by visiting:
https://sourceforge.net/tracker/?func=3Ddetail&atid=3D112580&aid=3D141758=
3&group_id=3D12580
Please note that this message will contain a full copy of the comment=20
thread, including the initial issue submission, for this request, not jus=
t=20
the latest update.
Category: CPU model
Group: None
Status: Open
Resolution: Fixed
Priority: 5
Submitted By: Nobody/Anonymous (nobody)
Assigned to: Stanislav Shwartsman (sshwarts)
Summary: Interrupt behaviour changed from 2.2.1 to 2.2.5
Initial Comment:
I'm rewriting my hobby OS to include SMP support. I've been using bochs=20
2.2.1 with 4 processors as a development test machine.
I believe that the local APIC timer interrupt is not being delivered to t=
he=20
local CPU in bochs 2.2.5 for any processors.
The Intel documentation says the following: "The local APIC timer can be=20
programmed to send a local interrupt to its associated processor when a=20
programmed count is reached." (Section 8.1)
Since the APIC timer is regarded as a local interrupt, it gets delivered =
to=20
the processor core as described by the LVT. You are not able to specify t=
he=20
target CPU of the interrupt in the LVT - it goes to the core. So, the=20
interrupt shouldn't go missing or stray to another CPU...
My scheduler relies on the local APIC interrupt in order to do it's thing=
.=20
This interrupt never occurs in the 2.2.5 version of bochs compiled with 2=
=20
and 4 processors (I have not tested 8).
I've attached a floppy image which works on real hardware and 2.2.1. It=20
doesn't work on 2.2.5.
If you run on real harware or 2.2.1, you'll notice the
following:
1. The scheduler of each CPU runs and increments a character on screen on=
=20
line 5/6 ish. Each scheduler takes the character alongside the other.
2. The idle thread increments the first character on the screen. This idl=
e=20
thread will be running on all but the first CPU.
3. An userland init application increments a character further to the lef=
t=20
on the screen.
If you run it on 2.2.5, you'll see the following:
1. The userland application increments a character further to the left. T=
his=20
runs forever on the one CPU because it is never interrupted.
2. A single character increment once-ish in the first character on screen=
.=20
This is the idle thread's first loop. The idle thread looks like this:
((char*)0xB8000)[0]++; // Increment screen char.
asm ("hlt"); // Processor halt, wait interrupt.
As you can see, after the initial increment, the CPU hlt's and waits for =
an=20
interrupt which never arrives.
So whether it's a general interrupt problem on SMP bochs or just the loca=
l=20
APIC, there's something amiss.
Durand.
clutter (at) djm dot co dot za
Configuration command line:
./configure --prefix=3D$INSTALLPATH --enable-sep
--enable-processors=3D4 --enable-apic --enable-vbe --enable-4meg-pages --=
enable-global-pages
--enable-cpu-level=3D6
----------------------------------------------------------------------
>Comment By: Stanislav Shwartsman (sshwarts)
Date: 2006-01-30 15:52
Message:
Logged In: YES
user_id=3D487634
In 2.2.5 release the APIC timer was broken but in 2.2.6 the interrupt is=20
working. I reopened the bug report because of your request in mailing lis=
t=20
but now I am going to close it back as 'not a bug' or 'user error'.
I checked you test on 2.2.6 and found that timer interrupt is working=20
correctly. You never seen them because Bochs
2.2.5 implemented software disabling of local apic vs 2.2.1 release.
Read this:
When the APIC software enable/disable flag in the spurious interrupt vect=
or=20
register has been explicitly cleared, the local APIC is temporarily disab=
led=20
(see Section 8.4.3, "Enabling or Disabling the Local APIC"). The operatio=
n=20
and response of a local APIC while in this software- disabled state is as=
=20
follows:
* The local APIC will respond normally to INIT, NMI, SMI, and SIPI messag=
es.
* Pending interrupts in the IRR and ISR registers are held and require=20
masking or handling by the CPU.
* The local APIC can still issue IPIs. It is software=C3=A2=E2=82=AC=E2=84=
=A2s responsibility to=20
avoid issuing IPIs through the IPI mechanism and the ICR register if send=
ing=20
interrupts through this mechanism is not desired.
* The reception or transmission of any IPIs that are in progress when the=
=20
local APIC is disabled are completed before the local APIC enters the=20
software-disabled state.
* The mask bits for all the LVT entries are set. Attempts to reset these=20
bits will be ignored.
* (For Pentium and P6 family processors) The local APIC continues to list=
en=20
to all bus messages in order to keep its arbitration ID synchronized with=
=20
the rest of the system.
>>>>>>>>>>>>
=C3=A2=E2=82=AC=C2=A2 The mask bits for all the LVT entries are set. Atte=
mpts to reset these=20
bits will be ignored.
On power on and reset local apic in software disabled state=20
(spurious_interrupt_register =3D 0xff) and all above is applicable to you=
. You=20
are configuring LVT for software disabled APIC and it remains masked=20
forever - the timer interrupt will never be generated and it is correct=20
behavior.
This is log for APIC debug messages for your kernel:
00193998554i[APIC1] CPU 1 started up at 7C00:00000000 by APIC=20
00197090364i[APIC1] CPU 1: wrote 00010050 to TIMER LVT
(enabled=3D0)
00197090369i[APIC1] CPU 1: set timer divide factor to 16 00197560604i[API=
C1]=20
CPU 1: wrote 00010000 to TIMER LVT
(enabled=3D0)
00197560619i[APIC1] CPU 1: set timer divide factor to 128=20
00197603334i[APIC1] CPU 1: wrote 00010050 to TIMER LVT
(enabled=3D0)
00197626379i[APIC1] CPU 1: one shot mode - timer interrupt is masked=20
00197626379i[APIC1] CPU 1: local apic timer (one-shot) triggered int=20
00198385594i[APIC0] CPU 0: wrote 00010050 to TIMER LVT
(enabled=3D0)
00198385599i[APIC0] CPU 0: set timer divide factor to 16 00198855834i[API=
C0]=20
CPU 0: wrote 00010000 to TIMER LVT
(enabled=3D0)
00198855849i[APIC0] CPU 0: set timer divide factor to 128=20
00199414724i[APIC0] CPU 0: wrote 00010050 to TIMER LVT
(enabled=3D0)
00199437764i[APIC0] CPU 0: one shot mode - timer interrupt is masked=20
00199437764i[APIC0] CPU 0: local apic timer (one-shot) triggered int
It might work in real hardware because you have very nice MP aware BIOS=20
which leave you APIC in software enabled state when your kernek begins to=
=20
run. Bochs BIOS is not so nice to you and doesn't ;)
Stanislav
P.S. Next time please register when you submit a bug report when SourceFo=
rge=20
will mail you when your bug report was changed or closed. Bug reports nev=
er=20
disappear, but they sometimes getting closed and when you have to choose=20
specific option in the tracker to see it !
----------------------------------------------------------------------
Comment By: Stanislav Shwartsman (sshwarts)
Date: 2006-01-30 15:21
Message:
Logged In: YES
user_id=3D487634
Reopened by request from mailing list.
----------------------------------------------------------------------
Comment By: Stanislav Shwartsman (sshwarts)
Date: 2006-01-28 23:04
Message:
Logged In: YES
user_id=3D487634
Yes, it is known problem. It was figured out immediatelly (next day) afte=
r=20
the 2.2.5 release.
This is the brief description of the problem reason:
"The APIC timer is registered in the constructor of the local apic and th=
is=20
is too early. The apic constructor code is executed before all the code i=
n=20
main.cc. The bx_pc_system_c contructor is executed later and deletes all=20
registered timers during its initialization.
The bug also was fixed immediatelly. CHANGES list from 2.2.6
release:
- critical APIC timer bug fixed (Volker Ruppert)
I even would not check you example, I am sure the issue already fixed in=20
2.2.6 release. BTW 2.2.6 release should be released in the beginning on n=
ext=20
week based on current CVS code. So you could download and compile latest =
CVS=20
snapshot from Bochs website or just wait several days until you could=20
download precompiled release.
BTW, in spite of "patch release" version numeration the
2.2.6 release could be defined as first major SMP release.
The local APIC, PIC and I/O APIC code was significantly modified to suppo=
rt=20
up to 255 CPU in SMP configuiration (XAPIC model). New option added which=
=20
allows to set up number of emulated CPUs from .bochsrc and not during=20
configure/compile time. BTW, I posted messages about it into mailing list=
=20
and expected that people playing with the feature already before official=
=20
release ...
Stanislav
----------------------------------------------------------------------
You can respond by visiting:
https://sourceforge.net/tracker/?func=3Ddetail&atid=3D112580&aid=3D141758=
3&group_id=3D12580
-----Original Message-----
From: bochs-developers-admin@...
[mailto:bochs-developers-admin@...] On Behalf Of Durand=
=20
Miller
Sent: Monday, January 30, 2006 2:11 PM
To: bochs-developers@...
Subject: Re: [Bochs-developers] Interrupts appear broken for SMP in 2.2.5
ditto for 2.2.6. No interrupts occur...
Durand.
> Hi,
>
> http://www.djm.co.za/spoon/smp-int-bug-2.2.5.tar.gz
>
> This is a floppy image which works on real hardware and bochs 2.2.1. I=
t
> does not work on 2.2.5. The floppy image initializes all CPU's in a
> system and uses the local APIC timer interrupt to multitask. However it
> appears that the interrupts never fire in 2.2.5 or they go missing.
>
> I posted this initially on the Bug Report section of the website but it
> disappeared within minutes.
>
> This is my compilation configuration commands:
>
> --enable-sep --enable-processors=3D4 --enable-apic --enable-vbe
> --enable-4meg-pages --enable-global-pages --enable-cpu-level=3D6
>
> The configuration file is included in the tarball.
>
> I've tested this on Bochs 2.2.5 for 1 CPU, 2 CPU and 4 CPU systems. All
> configurations fail. Bochs 2.2.1 works without any problems.
>
> Let me know if you need any more information.
>
> Durand.
|
