Thanks :) I explicitly software-enable the APIC and it works now. This i=
the correct behaviour, as you pointed out.
The code worked on all of my machines here so I was confused. It appears
that they all enable the local APIC before booting the system. The bochs
BIOS leaves it disabled in 2.2.6, as per the Intel documents.
----- Original Message -----=20
From: "Stanislav Shwartsman" <stl@...>
To: <clutter@...>; <bochs-developers@...>
Sent: Monday, January 30, 2006 19:39
Subject: RE: [Bochs-developers] Interrupts appear broken for SMP in 2.2.5
Read the following mail. Please fix your kernel and confirm closing of th=
Bugs item #1417583, was opened at 2006-01-28 22:44 Message generated for=20
change (Comment added) made by sshwarts You can respond by visiting:
Please note that this message will contain a full copy of the comment=20
thread, including the initial issue submission, for this request, not jus=
the latest update.
Category: CPU model
Submitted By: Nobody/Anonymous (nobody)
Assigned to: Stanislav Shwartsman (sshwarts)
Summary: Interrupt behaviour changed from 2.2.1 to 2.2.5
I'm rewriting my hobby OS to include SMP support. I've been using bochs=20
2.2.1 with 4 processors as a development test machine.
I believe that the local APIC timer interrupt is not being delivered to t=
local CPU in bochs 2.2.5 for any processors.
The Intel documentation says the following: "The local APIC timer can be=20
programmed to send a local interrupt to its associated processor when a=20
programmed count is reached." (Section 8.1)
Since the APIC timer is regarded as a local interrupt, it gets delivered =
the processor core as described by the LVT. You are not able to specify t=
target CPU of the interrupt in the LVT - it goes to the core. So, the=20
interrupt shouldn't go missing or stray to another CPU...
My scheduler relies on the local APIC interrupt in order to do it's thing=
This interrupt never occurs in the 2.2.5 version of bochs compiled with 2=
and 4 processors (I have not tested 8).
I've attached a floppy image which works on real hardware and 2.2.1. It=20
doesn't work on 2.2.5.
If you run on real harware or 2.2.1, you'll notice the
1. The scheduler of each CPU runs and increments a character on screen on=
line 5/6 ish. Each scheduler takes the character alongside the other.
2. The idle thread increments the first character on the screen. This idl=
thread will be running on all but the first CPU.
3. An userland init application increments a character further to the lef=
on the screen.
If you run it on 2.2.5, you'll see the following:
1. The userland application increments a character further to the left. T=
runs forever on the one CPU because it is never interrupted.
2. A single character increment once-ish in the first character on screen=
This is the idle thread's first loop. The idle thread looks like this:
((char*)0xB8000)++; // Increment screen char.
asm ("hlt"); // Processor halt, wait interrupt.
As you can see, after the initial increment, the CPU hlt's and waits for =
interrupt which never arrives.
So whether it's a general interrupt problem on SMP bochs or just the loca=
APIC, there's something amiss.
clutter (at) djm dot co dot za
Configuration command line:
./configure --prefix=3D$INSTALLPATH --enable-sep
--enable-processors=3D4 --enable-apic --enable-vbe --enable-4meg-pages --=
>Comment By: Stanislav Shwartsman (sshwarts)
Date: 2006-01-30 15:52
Logged In: YES
In 2.2.5 release the APIC timer was broken but in 2.2.6 the interrupt is=20
working. I reopened the bug report because of your request in mailing lis=
but now I am going to close it back as 'not a bug' or 'user error'.
I checked you test on 2.2.6 and found that timer interrupt is working=20
correctly. You never seen them because Bochs
2.2.5 implemented software disabling of local apic vs 2.2.1 release.
When the APIC software enable/disable flag in the spurious interrupt vect=
register has been explicitly cleared, the local APIC is temporarily disab=
(see Section 8.4.3, "Enabling or Disabling the Local APIC"). The operatio=
and response of a local APIC while in this software- disabled state is as=
* The local APIC will respond normally to INIT, NMI, SMI, and SIPI messag=
* Pending interrupts in the IRR and ISR registers are held and require=20
masking or handling by the CPU.
* The local APIC can still issue IPIs. It is software=C3=A2=E2=82=AC=E2=84=
=A2s responsibility to=20
avoid issuing IPIs through the IPI mechanism and the ICR register if send=
interrupts through this mechanism is not desired.
* The reception or transmission of any IPIs that are in progress when the=
local APIC is disabled are completed before the local APIC enters the=20
* The mask bits for all the LVT entries are set. Attempts to reset these=20
bits will be ignored.
* (For Pentium and P6 family processors) The local APIC continues to list=
to all bus messages in order to keep its arbitration ID synchronized with=
the rest of the system.
=C3=A2=E2=82=AC=C2=A2 The mask bits for all the LVT entries are set. Atte=
mpts to reset these=20
bits will be ignored.
On power on and reset local apic in software disabled state=20
(spurious_interrupt_register =3D 0xff) and all above is applicable to you=
are configuring LVT for software disabled APIC and it remains masked=20
forever - the timer interrupt will never be generated and it is correct=20
This is log for APIC debug messages for your kernel:
00193998554i[APIC1] CPU 1 started up at 7C00:00000000 by APIC=20
00197090364i[APIC1] CPU 1: wrote 00010050 to TIMER LVT
00197090369i[APIC1] CPU 1: set timer divide factor to 16 00197560604i[API=
CPU 1: wrote 00010000 to TIMER LVT
00197560619i[APIC1] CPU 1: set timer divide factor to 128=20
00197603334i[APIC1] CPU 1: wrote 00010050 to TIMER LVT
00197626379i[APIC1] CPU 1: one shot mode - timer interrupt is masked=20
00197626379i[APIC1] CPU 1: local apic timer (one-shot) triggered int=20
00198385594i[APIC0] CPU 0: wrote 00010050 to TIMER LVT
00198385599i[APIC0] CPU 0: set timer divide factor to 16 00198855834i[API=
CPU 0: wrote 00010000 to TIMER LVT
00198855849i[APIC0] CPU 0: set timer divide factor to 128=20
00199414724i[APIC0] CPU 0: wrote 00010050 to TIMER LVT
00199437764i[APIC0] CPU 0: one shot mode - timer interrupt is masked=20
00199437764i[APIC0] CPU 0: local apic timer (one-shot) triggered int
It might work in real hardware because you have very nice MP aware BIOS=20
which leave you APIC in software enabled state when your kernek begins to=
run. Bochs BIOS is not so nice to you and doesn't ;)
P.S. Next time please register when you submit a bug report when SourceFo=
will mail you when your bug report was changed or closed. Bug reports nev=
disappear, but they sometimes getting closed and when you have to choose=20
specific option in the tracker to see it !
Comment By: Stanislav Shwartsman (sshwarts)
Date: 2006-01-30 15:21
Logged In: YES
Reopened by request from mailing list.
Comment By: Stanislav Shwartsman (sshwarts)
Date: 2006-01-28 23:04
Logged In: YES
Yes, it is known problem. It was figured out immediatelly (next day) afte=
the 2.2.5 release.
This is the brief description of the problem reason:
"The APIC timer is registered in the constructor of the local apic and th=
is too early. The apic constructor code is executed before all the code i=
main.cc. The bx_pc_system_c contructor is executed later and deletes all=20
registered timers during its initialization.
The bug also was fixed immediatelly. CHANGES list from 2.2.6
- critical APIC timer bug fixed (Volker Ruppert)
I even would not check you example, I am sure the issue already fixed in=20
2.2.6 release. BTW 2.2.6 release should be released in the beginning on n=
week based on current CVS code. So you could download and compile latest =
snapshot from Bochs website or just wait several days until you could=20
download precompiled release.
BTW, in spite of "patch release" version numeration the
2.2.6 release could be defined as first major SMP release.
The local APIC, PIC and I/O APIC code was significantly modified to suppo=
up to 255 CPU in SMP configuiration (XAPIC model). New option added which=
allows to set up number of emulated CPUs from .bochsrc and not during=20
configure/compile time. BTW, I posted messages about it into mailing list=
and expected that people playing with the feature already before official=
You can respond by visiting:
[mailto:bochs-developers-admin@...] On Behalf Of Durand=
Sent: Monday, January 30, 2006 2:11 PM
Subject: Re: [Bochs-developers] Interrupts appear broken for SMP in 2.2.5
ditto for 2.2.6. No interrupts occur...
> This is a floppy image which works on real hardware and bochs 2.2.1. I=
> does not work on 2.2.5. The floppy image initializes all CPU's in a
> system and uses the local APIC timer interrupt to multitask. However it
> appears that the interrupts never fire in 2.2.5 or they go missing.
> I posted this initially on the Bug Report section of the website but it
> disappeared within minutes.
> This is my compilation configuration commands:
> --enable-sep --enable-processors=3D4 --enable-apic --enable-vbe
> --enable-4meg-pages --enable-global-pages --enable-cpu-level=3D6
> The configuration file is included in the tarball.
> I've tested this on Bochs 2.2.5 for 1 CPU, 2 CPU and 4 CPU systems. All
> configurations fail. Bochs 2.2.1 works without any problems.
> Let me know if you need any more information.