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  Blowfish VHDL Core

  BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.

  3 weekly downloads
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  FreeCores

  FreeCores is a project to provide and foster a place for the sharing and development of hardware designs, in the spirit of freedom, starting with all the Free Hardware cores moved from OpenCores.org, and indexed at FreeCores.org.

  1 weekly downloads
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  OS561/Minon/Kodek

  The OS561 operating system based around FORTH/Java. The OS is to run on a VHDL chip OpenHardware design called the Minon, but could become available for other platforms. The unique point of the design is a revolutionary data compression technology.

  1 weekly downloads
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  The SBus (Synergy Bus) Project

  The SBus is a family of high-speed packet-based databus standards, suitable for both networking and interdevice communication. They are optimized for high data density transactions. This project creates and documents the standards, schematics, and driver

  1 weekly downloads
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  SystemC Logic Analyzer

  HW(VHDL) and SW of logic analyzer and On-Chip-Verification(OCV) for Value Change Dump(VCD) file format that exported to seemd SystemC ,ModelSIM, and many other EDA tools. Very easy and Simple.

  0 weekly downloads
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  inter-software interface snippets

  xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.

  0 weekly downloads