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This project implements a reduced instruction set (RISC) CPU in VHDL. It was designed for the Altera Flex10k20 chip, but the VHDL code should port to any compatable chip. The instruction set is extensive, and the design is easily extendable to 16 bits.1 weekly downloads
The SXMMIL project aims at producing a toolset for helping Man-Machine developers to describe their MMI rather than code them. All the work is based on XML: the provided DTD will help concentrate on the logical view of MMI rather than its physical view.1 weekly downloads