OSI-Approved Open Source (103)
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- Artificial Intelligence
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- Programming Language: VHDL/Verilog ×
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
Code and documentation for the PSU Mars Society Rover
Palette for computer architecture design
A simple processor which has an 8-bit data bus and a 13 bit address bus. The memory is 8192 x 8, instructions are 8 or 16 bits wide, and all opcodes are 3 or 4 bits wide.
Ray Tracing micro-processor RTMP. Features: * Programmable pixel shaders. * SIMD 32-bit ALU. * Hardware support for Octree scene traversal. * Ray intersection cache. * Support for mutiple instances of RTMP working concurrently.
Collection of VHDL libraries for ASIC/FGPA development
What would verilog code translated to unlambda look like? This question has puzzled me for a long time and I've decided to do a unlambda backend to my c->verilog compiler. Come to think of it, why stop at unlambda? I will go all the way to NAND gates.
Susara is a development architecture for software-defined radio (SDR) applications. It assists developers to focus on the high-level design of radio components, from which efficient platform-specific source code is automatically generated.
VHDL description of a FPGA-based FBG interrogation system
Oscilloscope using a VGA monitor and a cpld
The VHDL Lookup Table Generator generates a table in vhdl from a C++-table. I was too lazy to write a parser. Code is found in the CVS (scroll down for url): http://vhdl-lut-gen.cvs.sourceforge.net/*checkout*/vhdl-lut-gen/vhdl-lut-gen/vhdl-lut-gen.cpp
Tool-independent Makefile generator for VHDL models.
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
This project aims to generate video signal using an FPGA development board
Tools and libraries for use with systemc and verilog
The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA
Digital waveform viewer/editor. eWave is a visual waveform timing editor compatible with VCD format (with image export possibilities) intended to be used in educational or technological (digital design) purposes. It is distributed as an Eclipse plugin.
xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.
Provides a simple way to interact with icarus verilog tool.
The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
SEL for access verilog via PLI/VPI API. Tested with Icarus Verilog.
Linuxware is a hardware architechture that implements many linux system calls natively in hardware, to improve performance.
mov86 is a free soft-core processor written in VHDL. The aim of the project is to develop a CPU-core with maximum compatibility to intel x86 architecture.
Open Source Hardware For Industrial Automation