- OS: Grouping and Descriptive Categories ×
Electronic Design Automation (EDA)
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ours This a print circuit board editor written in Qt. It aims to provide sprint layout like functionalities. It is not actually fonctional at this time, even as an alpha release but I will update my work regularly.
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xstools This project has been abandoned. Please go to https://github.com/xesscorp for current open source offerings from XESS Corp.
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ICanCAD Schemata A Schematic Entry system for rapid analog circuit development
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AutoGRAF Filterberegningsprogram, som kan beregne frekvenskurver for elektroniske filtre. Man tegner et diagram over kredsløbet og indsætter komponentværdier. Herefter kan programmet automatisk tegne frekvenskurver for kredsløbet Programmet er lavet i Xbasic
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gent Visualization of PCB (printed circuit board) descriptions in Gerber RS-274X format. The intention is to let a PCB designer take an RS-274X formatted file and generate a 3D concept view, either locally, or generated as PNG/clip, or browsable X3D/VRML.
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flosslogic IMPORTANT: The flosslogic project has merged with the sigrok project. Development continues in the sigrok wiki, mailing lists, IRC channel, and git repository.
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rfMaxima rfMaxima is an RF toolbox for the wxMaxima computer algebra system.
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LSim LSim is a software for simulation and make executables to ARM Cortex-M3 mcu from logic gates diagram. LSim can compile logic gates diagram and generate binary executable files (*.bin, *.hex) for cortex-m3 mcu´s (LPC1768, under development).
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aRTOS aRTOS is a SystemC library providing an abstract model of a real-time operating system (RTOS) for fast and accurate simulation of embedded HW/SW systems.
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PLP PLP stands for PerL Preprocessor. Perl is used as "control language" but can be used with any target/output language (C, C++, Java, Verilog, VHDL, plain text etc) The code is generated by embedding escaped Perl commands in your input file as needed
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SmGen SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.
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SPChart SPChart is free software to plot S-paramters from touchstone format(SNP)
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OpenSce This project aims to develop an opensource software with an attractive and efficient GUI which allows to design linear electronic circuits and to characterize existing ones.
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Lossi Lossi (LOgikSchaltungsSImulator - german for "logic circuit simulator"). It simulates logic circuits. Really.
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PEAMF Framework for the Analysis and Modification of EDIF netlists (FAME) is a C++ framework, developed at Politecnico di Torino, aimed at automating the analysis and modification of complex circuit netlists described in the standard EDIF 2.0.0 language.
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Tiny MiniLA Logic Analyzer Low cost version of MiniLA project. The only difference is that TiniLA board is assembled with XC95144XL. Thus, less features is available...
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CoreTML framework CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).
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QSapecNG QSapecNG is a Qt-based symbolic analysis program for linear analog circuits. In fact, it consists of two indipendently parts: the SapecNG framework engine, and the application gui QSapecNG.
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Rosana - Controladora de Dispositivo Este projeto visa controlar através da porta serial um dispositivo. compatível com hardware da Robotica Simples, porem pode ser modificado para qualquer outro produto serial. O Hardware atendido é a placa controladora de 8 reles.
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Ligaled Projeto para controle da porta paralela em Linux. Este projeto pode ser utilizado como integrador em projetos de robotica ou automação industrial. Funciona na console e permite integração com diversas linguagens como java/php/c++ entre outras.
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lilpM32 lilpM32 is a MIPS-like processor designed in Logisim, assembler program and documentation for them. Complete assembler and fully functional instruction set with I/O and subroutines features allow to write full-blown complicated programs.
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gedif Linux command to create and manipulate edif files, the edif files can be created from xml description or vhdl files, gedif command can make the schematic and behavioral description until the pcb description by automatic or manual routing function.
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VTDL - Virtual Technological Dev. Lab VTDL is a Virtual Technological Development Lab, VTDL, is OS independant and web based. this programs intent is to use MMO's and the internet in a new way, we will construct a virtual online lab environment, with working physics and machine tools
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Gschem-finalizer Integrator for gEDA (GPL EDA) Suites & Bridge gEDA to Kicad
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eagle-ipc7351 IPC-7351 footprint generator script for CadSoft's EAGLE PCB design/layout software. The goals of the project are to enable XML & GUI based footprint generation using the IPC-7351 calculation vectors.
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