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Python based binding for Data Acquisition from Data acquisition hardwares. with this one can access hardware just like c++ inportb() and outportb() and extra stuff..0 weekly downloads
Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.0 weekly downloads
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.0 weekly downloads