Electronic Design Automation (EDA)
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Universal JTAG library, server and tools UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements.
159 weekly downloads -
gputils gputils is a collection of tools for Microchip PIC microcontrollers. Its goal is to be fully compatible with Microchip's tools, MPASM, MPLINK, and MPLIB.
185 weekly downloads -
Electronic Engineering Tool A very usefull tool when working with electronics, from amature to engineer, ex. Converter: Fahrenheit-Celsius-Kelvin, Dec-Hex-Bin-Oct, etc. Calculator: Ohms Law, Coil Reactance, Capacitor Reactance, Thermal Resistant (C/W), Decibel (dB) etc.
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CapsimTMK Capsim(r) C Text Mode Kernel(TMK),DSP and communication blocks, topologies, libraries and tools for the development of high performance block diagram digital signal processing and communications systems,built in interpreter for scripting.SystemC support.
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Eagle Technology Data Acquisition Libraries, documentation, examples & drivers for Eagle Technology South Africa's Data Acquisition products. These include ISA, PCI, PCI Express, USB, Serial & Ethernet. Supported languages will be C/C++, JAVA, Perl, Python.
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Source Navigator for Verilog Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav
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BoardStatus Boardstatus is a Web-CGI/Postgresql database to manage electronic prototypes, including butch lists, notes, and and parameters. Support for users with different authorizations is included.
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CDL cycle language, compiler, simulator Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.
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PLP PLP stands for PerL Preprocessor. Perl is used as "control language" but can be used with any target/output language (C, C++, Java, Verilog, VHDL, plain text etc) The code is generated by embedding escaped Perl commands in your input file as needed
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Rotary clock layout tools a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.
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Skidbladnir toolbox with information and programs for Computer Aided Innovation The scientific background of Skidbladnir is known as the Theory of Inventive Problem Solving; in English abbreviated as TIPS or TRIZ, in German as TRIS.
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SmGen SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.
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Synopsys Consultant Script Repository An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.
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VTracer VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.
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Carrion This is an ECAD toolkit for building programs and scripts to solve problems encounter in chip design.It currently addresses the layout, circuit and logic design areas.
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ChipVault ChipVault is a project organizer for VHDL and Verilog RTL hardware designs. It provides rapid hierarchy navigation and includes Revision Control and hooks to launching external tools. ChipVault is written in Perl and is small, fast and efficient.
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Extra Element Solver The purpose of this project is to create a framework for automatically computing , symbolically, low entry expressions for linear circuits using R.D. Middlebrook's Extra Element Theorem.
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Icarus Verilog Test Suite Provides a GPL'd test suite for verification of the verilog language. This project is affiliated with the Icarus Verilog compiler effort at icarus.com, and test reports are collected from that project.
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Reaper ECAD libraries Libraries for building tools and scripts for ECAD. Contains physical, circuit and Verilog libraries bolted into the 'carrion' module.
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V2000 Project Mixed Analog/Digital Simulator framework - parser and elaborator for Verilog and Verilog-AMS, and an extended C++ (ParC - http://parallel.cc) to be used as the simulation engine.
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Verilator Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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Virtual Hardware Interface A Hardware/Software Co-Simulation package utilizing TCP/IP networking to allow C and Perl based development simulation environments using Verilog or SystemC hardware models.
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zuphinx zuphinx (say zoo'finks) is an efficient VHDL design environment.
0 weekly downloads
