- Programming Language: Tcl ×
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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.7 weekly downloads
Various scripts for several EDA tools such as: RTL Compiler, spyglass, lec, temposync, etc. Scripts are useful in IC design.0 weekly downloads