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- Programming Language: Perl ×
Testing for modern techniques, algorithms and optimization methods.
This is a code generator used to generate HDL codes for LDPC decoder.
Magnetostatic finite differences simulation tool based on GNU Octave and a Perl/Tk user interface.
TCL and Perl scripts to help analyze structural properties of RTL within Synopsys Design Compiler suite.
PLP stands for PerL Preprocessor. Perl is used as "control language" but can be used with any target/output language (C, C++, Java, Verilog, VHDL, plain text etc) The code is generated by embedding escaped Perl commands in your input file as needed1 weekly downloads
Eng-DB-2 is a light-weight engineering database. It allows to manage components/assemblies and their associated AVLs and technical documentation, assemble BOMs for finished goods and annotate these with quotations received from suppliers.1 weekly downloads
a set of free tools and software aimed at design automation. SPICE ( NG-spice )MAGIC XCIRCUIT Main aim - to automate the layout of clock distribution on a chip, using rotary clock oscilation.1 weekly downloads
Libraries for building tools and scripts for ECAD. Contains physical, circuit and Verilog libraries bolted into the 'carrion' module.
Project to develop an open toolkit (primarily) for the design of power kites.2 weekly downloads
Source Navigator for Verilog is a verilog parser that allows Source Navigator to be used with the Verilog Hardware Description Language. http://sources.redhat.com/sourcenav1 weekly downloads
An online SSL (128-bit strong encryption) repository for scripts created and maintained by Synopsys Design Consultants.1 weekly downloads
Boardstatus is a Web-CGI/Postgresql database to manage electronic prototypes, including butch lists, notes, and and parameters. Support for users with different authorizations is included.2 weekly downloads
This is an ECAD toolkit for building programs and scripts to solve problems encounter in chip design.It currently addresses the layout, circuit and logic design areas.
Grid-tools is a collection of scripts to aid in the submission of complex jobs to either Sun Grid Engine or LSF.1 weekly downloads
VTracer is a Verilog Testbench developer aid. Contains well documented Verilog-Perl co-simulation environment (TCP sockets based), structural Verilog parser, demo Testbenches.1 weekly downloads
Language, compiler and simulator for CDL cycle description language Platforms: OSX, Linux, Cygwin CDL is a C-like language for hardware description; simulator generates C++ models and synthesizable verilog. Includes C++ cycle simulation engine.2 weekly downloads