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Netlist database and manipulation API with interfaces to Java and Ruby. Verilog netlist inputs are supported. Project branch continues to evolve: https://github.com/gburdell/nldb including addition of tclsh UI.2 weekly downloads
An EEChip is a chip whose software can evolve. It works like Conway\'s Game of Life, but with highly generic rules for each cell. This project simulates an EEChip in C, and the chips are tested, selected, and mutated in Ruby.0 weekly downloads
fhlow is a design environment that handles the design-flow of the digital hardware design process for VHDL desings on FPGAs. It supports Mentor Graphics Modelsim and Altera Quartus by now.0 weekly downloads