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PVSim is a Portable Verilog Simulator for Mac OSX, Linux, and Windows. It features a fast compile-simulate-display cycle. The core is in C++, and the GUI, wxPython.38 weekly downloads
Scanning Probe Microscopy Controller and Data Visualization Software11 weekly downloads
A programmable signal generator and RF synthesizer for scientific experiments, especially quantum computing and quantum information processing. It includes hardware, firmware, software, and documentation, all under an open source license.9 weekly downloads
Python Hardware Processor2 weekly downloads
This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.1 weekly downloads
Synthesia is an open hardware/software platform intended for creating standalone audio devices such as synthesizers on embedded processors.1 weekly downloads
A Development Framework for Coldfire
The decimation Tools Set (DTS) generate automatically efficient implementations of Linear Feedback Shift Registers (LFSRs) in both software and hardware.
Frupo stands for Frugal Processor. The idea is to create a small footprint,implementation independent,soft core optimized for easy C programming. The project involves creation of the core itself as well as a toolchain to support it.
This project includes a set of tools and guidelines designed for rapid production of large-scale embedded systems projects. The tools enable quick generation of reusable, reconfigurable hardware, using a user-specified hardware description language.
Iterative implementation for finding shortest distance using kd trees
Labcoat; the VHDL graphic emulator.
The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
System on Chip design generator.
Common Lisp frontend to Verilog HDL -- use the Common Lisp macro system to generate reams of boring, ugly Verilog.