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Tools for FPGA development and IP cores. This project provides tools, cores and documentation to develope FPGA applications. The project focuses on VHDL.90 weekly downloads
HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL7 weekly downloads
SmGen is a finite state machine generator for Verilog. Not an FSM entry tool though. The input is behavioral-like Verilog. SmGen generates a synthesizabe FSM based design from it. Clock boundaries are explicitly provided by the designer.1 weekly downloads
Simple signal processing projects in Scilab and Matlab
The Verilog-Perl distribution provides Perl preprocessing, parsing and utilities for the Verilog Language. It is also available from CPAN under the Verilog:: namespace.
Meus arquivos de mestrado
This project is a collection of Open Source crypto cores and implementations relating to high speed cryptanalysis/cracking and complex implementations.
zuphinx (say zoo'finks) is an efficient VHDL design environment.