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upf2cpf is a cool command line tool which will takes in a UPF(Unified Power Format) and will convert it to a CPF(Common Power Format).This tool is very useful for Chip Design Engineers, who want to feed the power related info about the RTL in UPF/CPF.
Asynchronous Spatial Division Multiplexing Router for On-Chip Networks1 weekly downloads
Simple AVR OS2 weekly downloads
Configurable VHDL bitcoin miner that is AXI4 lite compliant
This project is an Adaptive LMS Equalizer / Filter implementation with piplined architecture for speedier performance.This project implements equalizer in VHDL so can be used with FPGA/CPLD
The Affordable BIOS Restoration Tool provides VHDL and C code to recover from failed BIOS upgrades using affordable CPLD's. EEPROM's and Flash chips can be restored with this flash programmer. Interfaces for DIP and tsop packages are being developed.1 weekly downloads
Holds all information related to creating an Agile Development Methodology geared towards ASIC/FPGA Verification.
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e1 weekly downloads
Library of Approximate Adders7 weekly downloads
An arbitrary waveform generator (AWG) is a piece of electronic test equipment used to generate any arbitrarily defined electrical waveform as it's output. This waveforms can be generated with MATLAB.
A arcade snake game purely written in verilog [ no asm or C ]26 weekly downloads
Sistema Operacional1 weekly downloads
BlowfishVHDL - free fully synthesizable Blowfish encryption algorithm hardware implementation.3 weekly downloads
Bluespec SystemVerilog Eclipse Plugin
Cell Matrix Model Simulator
A Development Framework for Coldfire
a micro processor 16 bits optimized to hold in a CPLD
Custom uav is a complete flight control system in development. The project includes everything required for unmanned flight.
This project aim to develop a suite of tool to ease the development of ASIC/FPGA solution. The final program should be an IDE enabling the creation and specification of a project from it's start to finish.
Multimedia communications require efficient and real-time implementations of multirate digital signal processing systems.
An operating system written in VHDL1 weekly downloads
CoreTML framework is an open-source template-based configuration system allowing the developer to create parametrized templates by inserting special content to any text files. Its main purpose is to serve as a toolkit for semiconductor IP core creation (based on VHDL/Verilog).14 weekly downloads
We are currently working with professors Bruce Land and Paul Kintner to develop a hardware mobile GPS receiver on an FPGA, capable of receiving L1 civilian GPS signals in real time.
Custom Architecture Generator Tool is a software based on the Netbeans Platform, the main purpose is to accelerate the embedded system realisation with a high level description: VHDL code,C2VHDL conversion,Quartus project generation,real time application1 weekly downloads
Simple signal processing projects in Scilab and Matlab