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- Programming Language: VHDL/Verilog ×
PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e2 weekly downloads
A methodology to create netlists for printed circuit board layout using a novel PCB specific HDL as the source language.
Open-source alternative partial reconfiguration flow for Xilinx FPGAs1 weekly downloads
The ixo.de USB JTAG pod and firmware allows to access JTAG-capable chips via USB and a protocol like Altera USB-Blaster.
Inane's not a NES emulator. It is a reimplementation of the original NES hardware in VHDL with the goal of making it fully synthesize in hardware.
Platform for advanced open source IP-Core development, i. e. dynamic memory controllers for FPGAs.
Este proyecto presenta GraphUIS, una implementación de un periférico de video en un FPGA como un diseño modular caracterizado por no tener memoria dedicada. Se desarrolló como un proyecto académico en la Universidad Industrial de Santander.5 weekly downloads
Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs such as Xilinx' Spartan3 and Virtex FPGAs.1 weekly downloads
Automatic build management for VHDL and Verilog projects. The automatic dependency resolver finds the exact subset of sources, and the correct order they must appear in required to build a project. A Makefile automates the actual build itself.
Yet Another DLX based Architecture System On a Chip (YADASOC) is a RTL Verilog implenetation of a DLX based CPU and subsystems.
An FPGA based system, using captured video as source of a basketball movement. Human movement is detected and translated into motion vectors to hit a virtual ball.
HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL5 weekly downloads
Development of a fully designed alarm clock implemented on the Xilinx Spartan3 board.
The project uses the infrared camera from the wiimote to track hand gestures. This tracking is performed on an Altera DE2-70 FPGA
Oscilloscope components, including 100MHz quad A/D, VHDL code for Xilinx FPGA, and driver for Octave or Matlab.2 weekly downloads
vorbis-hw is an open-source hardware implementation of an Ogg-Vorbis decoder. My current plan is to port the "tremor" codec to VHDL.
The system allows running and controlling the MAC controller on the Xilinx board with Virtex. This way the project provides a set of features and functionality to easy build the application and eCos and TCP/IP FreeBSD with access to Xilinx MAC controller1 weekly downloads
Oscilloscope using a VGA monitor and a cpld
A verilog language compiler written using Java and JavaCC. It produces a netlist, an ascii text file, of all the cell connections. It can compile very large circuits comprised of many modules.1 weekly downloads
Academic project of USB controller
simple and practical RISC Processor work in Altera DE2 Board(made by TERASIC)
Spartan3A Starter Kit Oscilloscope with Java Client1 weekly downloads
SHELLEY Software HardwarE Light LanguagE Yep !
A VHDL - Verilog SAD256 module
Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.