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PID_control, real_time, matlab_simulink, xilinx_ise, fpga_spartan3e1 weekly downloads
SystemVerilog module to substitute Verilog PLA system tasks.1 weekly downloads
Please see https://sourceforge.net/projects/smpla/?source=directory1 weekly downloads
Open RVC-CAL to HDL (ORC2HDL) is an Eclipse Plugin which uses the Open RVC-CAL Compiler (ORCC) and the openForge HDL Synthesizer. This plugin gives the ability to generate HDL code from a RVC-CAL model.
This is my personal sourceforge file for personal projects that I intend to work on.
cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
xswifs stands for: cross SoftWare Interfaces. This project provide examples (snippets) for interfacing various software tools and languages with various mechanism. It has been created to help in HW/SW co-simulation and to provide benchmarks.