Showing page 1 of 1.

• 
  PVSim Verilog Simulator

  PVSim is a Portable Verilog Simulator for Mac OSX, Linux, and Windows. It features a fast compile-simulate-display cycle. The core is in C++, and the GUI, wxPython.

  50 weekly downloads
• 
  pyCPU

  Python Hardware Processor

  3 weekly downloads
• 
  EveSoc

  This project's goal is to provide a simple but extendable SOC (System On Chip) that can be loaded into an FPGA in order to quickly test custom coprocessors and evaluate their robustness against SCA (Side Channel Attacks) or others physical attacks.

  1 weekly downloads
• 
  Orchestra, a SoC Generator

  The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.

  0 weekly downloads
• 
  verilisp

  Common Lisp frontend to Verilog HDL -- use the Common Lisp macro system to generate reams of boring, ugly Verilog.

  0 weekly downloads