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Showing 3 open source projects for "ahb"
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View all cloud assets of AWS, Google Cloud, Azure, Kubernetes, Digital Ocean in one place. Automates security misconfigurations of assets with guidance to resolve them. Covers far beyond basic checklists. It automatically evaluates the security misconfigs of the assets & provides step-by-step guidance to resolve them
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Define and Deliver Comprehensive Cybersecurity Services. Security threats continue to grow, and your clients are most likely at risk. Small- to medium-sized businesses (SMBs) are targeted by 64% of all cyberattacks, and 62% of them admit lacking in-house expertise to deal with security issues. Now technology solution providers (TSPs) are a prime target. Enter ConnectWise Cybersecurity Management (formerly ConnectWise Fortify) — the advanced cybersecurity solution you need to deliver the managed detection and response protection your clients require. Whether you’re talking to prospects or clients, we provide you with the right insights and data to support your cybersecurity conversation. From client-facing reports to technical guidance, we reduce the noise by guiding you through what’s really needed to demonstrate the value of enhanced strategy.
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stm32f030-lib
STM32F030 startup code and library
Use: flash_pre(1); // Flash prefetch flash_lat(1); // Flash latency ahb_div(AHB_DIV_1); // AHB divider apb_div(APB_DIV_1); // APB divider pll_on(0,4, F_CPU / (F_HSI/2)); // start PLL from HSI/2 sysclk_sel(SYSCLK_PLL); // select PLL ahb_on(AHB_GPIOA | AHB_GPIOB | AHB_GPIOF); // enable AHB clocks systick_on(F_CPU / 1000); // start SysTick @ 1000Hz wdt_start(1000); // start WDT @ 1sec pin_mode(GPIOA,5, MO_OUT, OT_PP,OS_2M,PU_NO); // pin config pin_wr(GPIOA,5, !pin_rd(GPIOA,5)); // pin invert -
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n32g430-lib
Nationstech N32G430 library/startup code
Nationstech N32G430 MCU library/startup code. Use: // set FLASH iCache, prefetch, latency flash_icache(1); flash_pref(1); flash_lat(3); // set AHB/APB1/APB2 dividers ahb_div(AHB_DIV_1); apb1_div(APB1_DIV_4); apb2_div(APB2_DIV_2); // start PLL pll_on(0,0, 0, 16); sclk_sel(SCLK_PLL); // enable peripherals clocks ahb_on(AHB_GPIOA | AHB_ADC | AHB_CRC); apb1_on(APB1_TIM2); apb2_on(APB2_AFIO | APB2_USART1); // configure pin mode/type/speed/pullup/output pin_mo(GPIOA,0, MO_OUT); pin_ot(GPIOA,0... -
3
bel_fft
FFT co-processor in Verilog based on the KISS FFT
... and the Wishbone bus are supported. However, bel_fft's architecture allows an easy adaptation to further bus architectures (e.g. AMBA AHB). It comes with a Java wizard to configure the co-processor and to generate all required files (e.g. twiddle ROMs). It comes with integration into Xilinx Vivado, EDK, and Altera QSYS and includes example designs for Xilinx Zynq and with PCI-Express core (including Linux driver and application). bel_fft is distributed under the GNU Lesser Public License 2.1.
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