Request For Comments >> RFC 5: Clock Board
Status: Gathering requirements
Initiate Date: 4 February 2010
Requestor: Hartmut Haeffner
Writer: Paul Pham
This requested board is for a compact clock source that combines the generation of clocks for driving the different boards in a pulse programmer.
Requirements
- Generation of a fast (800 MHz - 1 GHz) clock for DDS sampling
- Fanning out this sampling clock to multiple (up to 8) DDS boards
- Dividing down a slower (100 MHz) clock for running the FPGA sequencer, still synchronized to the above
- Generating all clocks from an external 10 MHz source
- Stability of 1e-9 (+/- 1 ns per second)
- SMA coax output
Use Case
Currently, the FPGA sequencer needs to write and read data to other devices on synchronized clocks. Many devices accept an incoming clock, which is the same as the sequencer clock, so there is no problem. The AD9744 digital-to-analog converter is one such device.
Divided-Down Clocks May Be Out-of-Phase
However, DDS chips from Analog Devices, such as the AD9858 and AD9910, take a faster clock to produce the digital samples that approximate a sinusoid, and produce an outgoing clock, which is divided down (by 8) for interacting with slower devices like the sequencer. However, the divided down clock from multiple DDS boards may be out-of-phase. If the DDS divided clock is not used, and instead another clock divider board is used to divide 800 MHz down to 100 MHz, then this is another potential clock mismatch. The 100 MHz clocks may be out of phase relative to one another, but they will still be synchronized with their underlying parent clock at 800 MHz. Therefore, no glitches or metastability will over, but the DDS boards will be one cycle ahead or behind of each other, depending non-deterministically on when they power up, initial noise conditions, and possibly manufacturing tolerances within the chip itself.
This may not be a huge problem, but the user should be aware that some DDS boards will not update on exactly the same (100 MHz, 10 ns) cycle. This problem is explicitly addressed in the AD9910, which contains inputs for synchronizing clocks across multiple boards. The problem simply must be tolerated on AD9858 boards.
Fanning Out
In a related use case, adding more RF channels (namely, DDS boards and associated amplifiers and modulators) or new devices will require even more synchronized clocks at various division or multiplication ratios. Furthermore, these will need to be synchronized with external devices via a slower external source (for example, 10 MHz). Therefore, any clock board will also need to be externally synchronized, contain an onboard crystal/oscillator for self-contained testing purposes, and also be able to fan-out clock outputs in a scalable way.
Jitter and Physical Constraints
The clock board should introduce minimal jitter into the system, since any noise in the clock is amplified in all devices downstream that depend on it. The clock board should also be physically compact to take up as little room as possible, minimize the amount of cabling, and also be correspondingly cheaper and easier to assemble and use.
Limitations of Current Approach
The following clock scheme is proposed by Boerge Hemmerling in his manual, Section 4.2, pages 9 through 10:
This approach relies on external Marconi synthesizers to supply the fast 800 MHz sampling clock and uses discrete Mini-Circuits RF power splitters to fan out the clock source. This scheme greatly improves on the naive original approach of passively splitting the divided down clock from an AD9858 DDS board. However, it also carries over some old limitations as well as introducing new ones.
- Adjustable GHz frequency synthesizers such as the Marconi are large, power-hungry, and expensive, and are only used to produce a single, fixed frequency (800 MHz or 1 GHz).
- Buying discrete Mini-Circuits RF parts are expensive. They are also bulky to mount inside a limited enclosure.
- Running short SMA cables between discrete components requires a minimum turning radius and also introduces space and cost constraints.
- The divided down 100 MHz clocks of individual DDS boards may still be out-of-sync, per the above discussion.
- The AD9513 clock divider board is overkill for simply dividing down a clock, and requires separate programming via a USB interface every time it powers on.
Design
The proposed design combines a compact GHz clock source with a clock divider and fanout chips, all on the same board with impedance-matched networks to filter out unwanted frequencies and also reflection noise.
It is based on the following scheme currently being used at UW Seattle, with clock programming by Jeff Booth.
http://pulsing.wordpress.com/2010/01/18/clock-programming/
Clock Source
The ADF-4360-4 chip on an EB1 Rev. D3 can be used to provide a clock within the range of 1.45 GHz to 1.75 GHz. It accepts an external reference, which on the evaluation board is provided by an on-board 10 MHz oscillator.
http://www.analog.com/en/rfif-components/pll-synthesizersvcos/adf4360-4/products/product.html
Related chips in the same line, (ADF-4360-x) can be selected to choose different frequencies. However, the choice of 1.6 GHz allows easy division to get 800 MHz (divide by 2) and 100 MHz (divide by 16).
This chip is great for a clock source, but the evaluation board presents several problems for production use:
- It depends on a +9V battery for power
- It must be programmed via a parallel cable and a Windows software interface.
These problems can be circumvented on a custom board which contains the following features:
- power connectors for the yellow box power supply board
- dedicated connection to a 2-wire serial programming interface
- such as the breakout board I2C lines, as in Jeff's blog post.
Clock Divider
The AD9517-4 clock divider board provides the option to divide down a 1.6 GHz clock to 800 MHz and 100 MHz. It has the advantage of being programmed by DIP switches, and not a separate serial / software interface.
It is much simpler and cheaper than the AD9513 board. However, it also contains a power limitation, in this case, an awkward SMA +3.3V connector. Seriously, why do people provide power over coax?
Again, a custom board can solve the power problem and also be made much more compact when combined with the other parts of the clock system.
Clock Fanout
To be decided. Whatever chip used should have the following characteristics:
- 8 outputs to match the power splitter approach
- LVDS clocks to allow synchronization with the AD9910
External Synchronization
The custom clock board should contain an on-board 10 MHz clock for self-contained testing, but also an easy way to switch to an external source for actual experiments.
